• Title/Summary/Keyword: Frame per second(FPS)

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Error Analysis of Flow Velocity Measured through Granular PIV Based on Interrogation Area, Frame Per Second, and Video Resolution (상관 영역과 초당 촬영 수와 해상도에 따른 Granular PIV에서의 유동 속도의 오차 분석)

  • Choi, Jongeun;Park, Junyoung
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.20 no.7
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    • pp.58-65
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    • 2021
  • Research on general particle image velocimetry (PIV) has been conducted extensively, but studies on granular PIV are relatively insufficient. In addition, the parameters used for analyzing granular PIV need to be optimized. In this study, we analyzed the error of velocity measurements based on the interrogation area (64-192 pixel), frame per second (30-120 FPS), and video resolution [ultrahigh definition (UHD) and high definition (HD)] within the velocity range typically measured in hoppers. The estimated errors of the granular PIV were below 5%, which is generally acceptable. However, considering the data reliability, the flow velocity in the hopper could be measured with less than 5% error at 120 FPS or higher in the HD resolution and 30 FPS or higher in the UHD resolution.

An Effective Structure of Hardware Compression for Potentially Visible Set of Indoor 3D Game Scenes (실내 3D 게임 장면의 잠재적 가시 집합을 위한 효과적인 하드웨어 압축 구조)

  • Kim, Youngsik
    • Journal of Korea Game Society
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    • v.14 no.6
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    • pp.29-38
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    • 2014
  • In the large scale indoor 3D game scenes, the data amount of potentially visible set (PVS) which pre-computes the information of occlusion culling can be huge. However, the large part of them can be represented as zero. In this paper, the effective hardware structure is designed, which compresses PVS data as the way of zero run length encoding (ZRLE) during building the scene trees of 3D games in mobile environments. The compression ratio of the proposed structure and the rendering speed (frame per second: FPS) according to both PVS culling and frustum culling are analyzed under 3D game simulations.

GPU-Accelerated Single Image Depth Estimation with Color-Filtered Aperture

  • Hsu, Yueh-Teng;Chen, Chun-Chieh;Tseng, Shu-Ming
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.8 no.3
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    • pp.1058-1070
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    • 2014
  • There are two major ways to implement depth estimation, multiple image depth estimation and single image depth estimation, respectively. The former has a high hardware cost because it uses multiple cameras but it has a simple software algorithm. Conversely, the latter has a low hardware cost but the software algorithm is complex. One of the recent trends in this field is to make a system compact, or even portable, and to simplify the optical elements to be attached to the conventional camera. In this paper, we present an implementation of depth estimation with a single image using a graphics processing unit (GPU) in a desktop PC, and achieve real-time application via our evolutional algorithm and parallel processing technique, employing a compute shader. The methods greatly accelerate the compute-intensive implementation of depth estimation with a single view image from 0.003 frames per second (fps) (implemented in MATLAB) to 53 fps, which is almost twice the real-time standard of 30 fps. In the previous literature, to the best of our knowledge, no paper discusses the optimization of depth estimation using a single image, and the frame rate of our final result is better than that of previous studies using multiple images, whose frame rate is about 20fps.

Influence of DIC Frame Rate on Experimental Determination of Instability and Fracture Points for DP980 Sheets under Various Loading Conditions (다양한 하중 조건에서 DP980 판재의 불안정성 및 파단점 결정시 DIC Frame Rate의 영향)

  • Noh, E.;Hong, S.
    • Transactions of Materials Processing
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    • v.28 no.6
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    • pp.368-374
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    • 2019
  • The past recent years have seen an increasing use of high-strength steel sheets in the automotive industry. However, the formability and damage prediction of these materials requires accurate acquisition of necking and fracture strains. Digital image correlation (DIC) is used to accurately capture the necking and fracture strains during testing. The fact that single time points of capturing vary with frame rate makes the need for an investigation necessary. For the high-strength steel DP980, the frame-rate dependences of the final necking and fracture strains values are analyzed here. To eliminate the influence of gauge length, the strains were measured locally by DIC. Results for three specimen shapes obtained with frame rates of 1 and 900 fps (frames per second) were considered and based on them, triaxiality failure diagrams (TFD) are established. It was observed that after diffuse necking, the deformation path departed from the initially linear one, and the stress triaxiality grew with ongoing deformation. It was further revealed that the frame rate-dependence of the necking strain was rather low (< 2%), whereas the fracture strain could be underestimated by up to 8% when the lower frame rate of 1 fps was used (compared with 900 fps). In this study, this issue is investigated while taking into consideration the three different triaxialities. These results demonstrate the importance of choosing an appropriate frame rate for the determination of necking and fracture strains in particular.

Detecting Digital Micromirror Device Malfunctions in High-throughput Maskless Lithography

  • Kang, Minwook;Kang, Dong Won;Hahn, Jae W.
    • Journal of the Optical Society of Korea
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    • v.17 no.6
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    • pp.513-517
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    • 2013
  • Recently, maskless lithography (ML) systems have become popular in digital manufacturing technologies. To achieve high-throughput manufacturing processes, digital micromirror devices (DMD) in ML systems must be driven to their operational limits, often in harsh conditions. We propose an instrument and algorithm to detect DMD malfunctions to ensure perfect mask image transfer to the photoresist in ML systems. DMD malfunctions are caused by either bad DMD pixels or data transfer errors. We detect bad DMD pixels with $20{\times}20$ pixel by white and black image tests. To analyze data transfer errors at high frame rates, we monitor changes in the frame rate of a target DMD pixel driven by the input data with a set frame rate of up to 28000 frames per second (fps). For our data transfer error detection method, we verified that there are no data transfer errors in the test by confirming the agreement between the input frame rate and the output frame rate within the measurement accuracy of 1 fps.

Prediction Based Dynamic Level of Detail in Flight Simulator (항공시뮬레이터에서 예측 기반의 동적 LOD 적용방안)

  • Kim, DongJin;Lim, Juho;Kim, Ki-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.7
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    • pp.1363-1368
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    • 2016
  • Fast rendering speed is one of key functions to provide realistic scenes in flight simulator. However, since flight simulator mostly operates with high volume terrain data, rendering speed is reduced and changed very rapidly when it handles file containing too much vertexs. So, previous schemes make use of Level of Details (LOD) scheme to prevent this problem. But, since LOD is applied after the large number of vertexs are detected, transition between scenes is not completely smooth. To solve this problem, in this paper, we propose a new dynamic LOD scheme which controls LOD level in advance through prediction of vertex overload. To verify the proposed scheme, we implement the proposed scheme in our flight simulation through OpenSceneGraph(OSG) and identify the reduced number of vertexs and enhanced Frame Per Second (FPS) by comparing real data with predicted one.

2500 fps High-Speed Binary CMOS Image Sensor Using Gate/Body-Tied Type High-Sensitivity Photodetector (Gate/Body-Tied 구조의 고감도 광검출기를 이용한 2500 fps 고속 바이너리 CMOS 이미지센서)

  • Kim, Sang-Hwan;Kwen, Hyeunwoo;Jang, Juneyoung;Kim, Young-Mo;Shin, Jang-Kyoo
    • Journal of Sensor Science and Technology
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    • v.30 no.1
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    • pp.61-65
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    • 2021
  • In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

Implementation of SA-DCT using a datapath (데이터패스를 이용한 SA-DCT 구현)

  • 박주현;김영민
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.5
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    • pp.25-32
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    • 1998
  • In this paper, SA (shape adaptive)-DCT is implemented using a datapath with 4 MACs (multiplication & accumulator). DCT is a well-known bottleneck of real-time video compression using MPEG-like schemes. High-speed pipelined MACs presented here implement real-time DCT. A datapath in this paper executes DCT/IDCT algorithms for QCIF 15fps(frame per second), maximum rate of VLBV(very low bitrte video) in MPEG-4. A 32bit accumulator in a MAC prevents distortion caused by fixed-point process. It can be applied to various operations such as ME (motion estimation) and MC(motion compensation) with a absolutor and a halfer.

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A Method for Generating Inbetween Frames in Sign Language Animation (수화 애니메이션을 위한 중간 프레임 생성 방법)

  • O, Jeong-Geun;Kim, Sang-Cheol
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.5
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    • pp.1317-1329
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    • 2000
  • The advanced techniques for video processing and computer graphics enables a sign language education system to appear. the system is capable of showing a sign language motion for an arbitrary sentence using the captured video clips of sign language words. In this paper, a method is suggested which generates the frames between the last frame of a word and the first frame of its following word in order to animate hand motion. In our method, we find hand locations and angles which are required for in between frame generation, capture and store the hand images at those locations and angles. The inbetween frames generation is simply a task of finding a sequence of hand angles and locations. Our method is computationally simple and requires a relatively small amount of disk space. However, our experiments show that inbetween frames for the presentation at about 15fps (frame per second) are achieved so tat the smooth animation of hand motion is possible. Our method improves on previous works in which computation cost is relativey high or unnecessary images are generated.

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Design of Architecture of Programmable Stack-based Video Processor with VHDL (VHDL을 이용한 프로그램 가능한 스택 기반 영상 프로세서 구조 설계)

  • 박주현;김영민
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.4
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    • pp.31-43
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    • 1999
  • The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

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