• Journal of electromagnetic engineering and science
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• v.11 no.3
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• pp.201-206
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• 2011

This paper presents a miniaturized epsilon negative (ENG) zeroth-order resonance (ZOR) patch antenna with an improved bandwidth. The miniaturization and the broad bandwidth of the ENG ZOR patch antenna are achieved by using a meandered via and a high permeability substrate instead of a straight via and a dielectric substrate. The use of a meandered via allows miniaturization of the ENG ZOR patch antenna without narrowing the bandwidth. The use of a high permeability substrate allows further miniaturization of the ENG ZOR patch antenna and improvement of the bandwidth. A high permeability substrate consisting of a multi-layered substrate is designed to have a small material loss. The antenna (kr=0.32) has a 10 dB fractional bandwidth of ~1 %, which is 1.74 times as broad as that of an antenna with a dielectric substrate.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.267-273
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• 2007

A fractional-N frequency synthesizer supports quadruple bands and multiple standards for mobile broadcasting systems. A novel linearized coarse tuned VCO adopting a pseudo-exponential capacitor bank structure is proposed to cover the wide bandwidth of 65%. The proposed technique successfully reduces the variations of KVCO and per-code frequency step by 3.2 and 2.7 times, respectively. For the divider and prescaler circuits, TSPC (true single-phase clock) logic is extensively utilized for high speed operation, low power consumption, and small silicon area. Implemented in $0.18-{\mu}m$ CMOS, the PLL covers $154{\sim}303$ MHz (VHF-III), $462{\sim}911$ MHz (UHF), and $1441{\sim}1887$ MHz (L1, L2) with two VCO's while dissipating 23 mA from 1.8 V supply. The integrated phase noise is 0.598 and 0.812 degree for the integer-N and fractional-N modes, respectively, at 750 MHz output frequency. The in-band noise at 10 kHz offset is -96 dBc/Hz for the integer-N mode and degraded only by 3 dB for the fractional-N mode.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.2 no.4
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• pp.10-16
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• 1991

A microstrip bandpass filter using stepped impedance resonators and tapped input / output is realized with Teflon substrate, whose center frequency is 3.5 GHz and fractional bandwidth is 20%. In order to realize a wider bandwidth of 30%, the Crystal's design method and the input / output tapping scheme are used. Another microstrip filter designed as mentioned above is realized with Epsilam-10 substrate. This case shows good agreement between the theoretical responses and the measured ones.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.581-585
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• 2013

A technique to expand the operating impedance bandwidth of a microstrip patch antenna is presented. The antenna is fed by a truncated T-shaped microstrip line on the ground plane with the rectangular slot. The proposed microstrip patch antenna offers wide bandwidth characteristics with the rectangular slot which has optimized size and position on the ground plane. The simulation result shows a fractional bandwidth of 127.8 %(0.65 to 2.95 GHz) at VSWR 2:1.

• Journal of electromagnetic engineering and science
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• v.8 no.4
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• pp.144-147
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• 2008

This paper proposes a tunable combline bandpass filter with high selectivity, constant bandwidth, and good stopband performances. A filter with these characteristics is obtained by applying cross-coupling to the conventional combline bandpass filter using stepped-impedance resonators(SIRs). For high selectivity and constant bandwidth, cross-coupling is utilized and the SIR configuration is used for enhanced stopband performances. The proposed combline tunable bandpass filter with 5% of fractional bandwidth at 1.6 GHz was fabricated and tested. The measured results showed 11.6% tunability with constant bandwidth, high selectivity and enhanced stopband characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.397-400
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• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.126-135
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• 2007

This paper proposes a new miniaturization method for a parallel coupled line filter with enhanced bandwidth characteristics. A previous method incorporated several advantages, such as size reduction through the use of only a small number of capacitors, in addition to grounding, suppression of harmonic characteristics, and improved skirt characteristics for the parallel coupled line filter, which is conventional in the field of RE filters due to its design and fabrication simplicity. However, the previous method also has disadvantages related to the bandwidth shrinkage of the miniaturized filters. In this paper, the amount of bandwidth shrinkage is analyzed in terms of the relationship between the loaded Q(quality factor) and the group delay of a resonator. Moreover, the reduction in the bandwidth is solved by a design with new design equations. To show the validity of the proposed method, a hairpin filter with a center frequency of 5.2 GHz and an fractional bandwidth(FBW) of 10% was scaled down to half its original dimension by the proposed method with the enhanced bandwidth characteristics. The measured result shows a high level of agreement with theoretical results.

• Journal of electromagnetic engineering and science
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• v.3 no.2
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• pp.104-110
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• 2003

A ring filter is proposed as a wide-banded filter. It consists of a ring and two short stubs, which are connected at 90$^{\circ}$ and 270$^{\circ}$ points of the ring. Since the termination impedance at 90$^{\circ}$ and 270$^{\circ}$ points of the ring and the characteristic impedance of the short stub have an effect on designing of it, the relation between them and bandwidths has been studied. Based on the study, two types of small-sized wideband CVT(constant VSWR-type impedance transformer)- and CCT(constant conductance-type impedance transformer)-ring filters are introduced, designed, simulated and one of two, a CCT -ring filter, is tested. The circumference of the ring can be reduced theoretically up to 60$^{\circ}$ and two of many cases having about 300$^{\circ}$ circumferences are simulated. The simulated results show more than 100 % fractional bandwidth, which can be obtained with more than 5 stages in conventional filter-design techniques. To test the designed CCT-ring filter, it has been fabricated in microstrip technology and the measured results show good agreement with the simulated ones, having more than 100 % fractional bandwidth.

• Journal of information and communication convergence engineering
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• v.21 no.1
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• pp.1-8
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• 2023

This paper presents a design method for a wideband bandpass filter (BPF) which compensates for frequency dependency based on the image admittance and image phase. In the proposed method, new compensation methods for the admittance and phase are integrated with the conventional method. The proposed method improves the frequency shift and reduces the unwanted bandwidth when designing more than 20% of the Fractional Bandwidth (FBW), whereas the conventional method exhibits frequency degradation at only 10% FBW. The proposed design theory was verified by applying it to both lumped elements and distributed lines through circuit simulation and measurements without an optimization process. The measurement results demonstrate improvements in the frequency shift and target bandwidth. In the future, an accurate design method based on frequency dependence can be implemented for the next-generation broadband communication system applications.