• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1322-1330
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• 1999

The major source of errors in high-speed networks such as Broadband ISDN(B-ISDN) is buffer overflow during congested conditions. These congestion errors are the dominant sources of errors in high-speed networks and result in cell losses. Conventional communication protocols use error detection and retransmission to deal with lost packets and transmission errors. As an alternative, we have presented a method to recover consecutive cell losses using forward error correction(FEC) in ATM(Asynchronous Transfer Mode) networks to reduce the problem. The method finds the lost cells by observing new cell sequence number($SN^{\ast}$). We have used the LI field together with SN and ST fields to consider the $SN^{\ast}$ which provides more correcting coverage than SN in ATM standards. The $SN^{\ast}$ based on the additive way such as the addition of LI capacity to original SN capacity is numbered a repeatedly 0-to-80 cycle. Another extension can be based on the multiplicative way such that LI capacity is multiplied by SN capacity. The multiplicative $SN^{\ast}$ is numbered in a repeatedly 0-to-1025 cycle.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.645-651
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• 2009

In this paper, we present bit error rate(BER) performance of an adaptive decision feedback equalizer(DFE) using experimental data. The experiment was performed at the shore of Geoje in November 2007. The BER of the adaptive DFE whose tap weight is updated by RLS is described with change of feedforward filter length, feedback filter length, training sequence length, and delay, which shows that the uncoded average BER is $4{\times}10^2\;and\;1.5{\times}10^{-2}$ with transmission range of 9.7km and 4km, respectively. The BER of the adaptive DFE can be lower than 10-3 by a forward error correction code and therefore the adaptive DFE may be a good candidate for a high speed AUV communications since the volume and weight of the underwater acoustic modem should be small because of the restricted space and power in the battery-operated AUV.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.4
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• pp.473-477
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• 2015

In this paper, a commercial phosphorescent white light-emitting diode (WLED) visible light communication (VLC) system with an equalization circuit to achieve the high modulation bandwidth was designed and demonstrated. An analytical method to examine the performance of the equalizer was carried out using a general circuit-simulator, PSpice. The equalization circuit was composed of two passive filters with resisters and a capacitor and an active filter with an op-amp. Utilizing our post-equalization technology, the ~3.5 MHz bandwidth of phosphor WLED could be extended to ~25 MHz without using an optical blue-filter. In this VLC system with a single round-type WLED and a single PIN photo-diode, ASK data transmission up to 35 Mbps at a 1m free space distance was obtained. The resulting bit-error-rate was $7.6{\times}10^{-4}$, which is less than the forward error correction (FEC) limit of $3.8{\times}10^{-3}$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.286-294
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• 2011

Cable modems typically are implemented by a forward error correction(FEC) scheme. The ITU-T Recommendation J-38 Annex B specifies using 64- and 256- quadrature amplitude modulation (QAM) and extended RS coding scheme. In implementing the cable modem, there are some problems to fabricate and fitting on FPGA chip. First, many clocks are needed in implementing cable modem because of different code rate and different modulation types. To reduce the number of clocks, we use the two memories, which are different clock speed for reading and writing data. Second, this system lost the bit-synchronization and frame-synchronization in decoder, the system recognize that all data is error. This paper solves the problems by using simple 5-stage registers and unique sync-word. Based on solutions for about problems, the cable modem is fabricated on FPGA chip name as Vertex II pro xc2vp30-5 by Xilinx, and we confirmed the effectiveness of the results.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.4
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• pp.67-73
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• 2002

There have been increased concerns on mobile stratospheric communication system(SCS) for the purpose of advanced service of personal and high speed communication systems. In fact, this SCS is considered and studied for IMT-2000 service by ITU. Although, it is important to make accurate channel model for prediction of the SCS performance, there is no measured channel data in this system. Thus, in this paper, we estimate the performance of SCS bye use of channel model provided by Corazza(2) and modified by You(3). And also, the effects of channel codings on system performance are analyzed by deriving bit error performance based on realistic Rician log-normal fading channel models. The performance results are divided into three kinds of areas with three kinds of elevation angles 20$^\cire$, 45$^\cire$, and 80$^\cire$. And also the effects of forward error correction channel codings on system performance with Hamming(7,4), HCH( IS,7) and convolutional code of constraint length 3 and code rate R=1/2.

• Journal of KIISE:Information Networking
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• v.31 no.4
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• pp.375-383
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• 2004

As wireless mobile networks have been widely adopted due to their convenience for deployment, the research for improving their performance has been actively conducted. Since their throughput is restrained by the packet corruption rate not by congestion as in wired networks, however, network simulations for performance evaluation need to select the appropriate wireless channel model representing the behavior of propagation errors for the evaluated channel. The selection of the right model should depend on various factors such as the adopted frequency band, the level of signal power, the existence of obstacles against signal propagation, the sensitivity of protocols to bit errors, and etc. This paper analyzes 10-day bit traces collected from real sensor channels exhibiting the high bit error rate to determine a suitable sensor channel model. For selection, it also evaluates the performance of two error recovery algorithms such as a link layer FEC algorithm and three TCPs (Tahoe, Reno, and Vegas) over several channel models. The comparison analysis shows that CM(Chaotic Map) model predicts 3-time less BER variance and 10-time larger PER(Packet Error Rate) than traces while these differences between the other models and traces are larger than 10-time. The simulation experiments, furthermore, prove that CM model evaluates the performance of these algorithms over sensor channels with the precision at least 10-time more accurate than any other models.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• KIPS Transactions on Computer and Communication Systems
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• v.10 no.2
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• pp.29-38
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• 2021

The Internet including mobile networks is developing to overcoming the limitation of physical distance and providing or acquiring information from remote locations. However, the systems that use video as primary information require higher bandwidth for recognizing the situation in remote places more accurately through high-quality video as well as lower latency for faster interaction between devices and users. The emergence of the 5th generation mobile network provides features such as high bandwidth and precise location recognition that were not experienced in previous-generation technologies. In addition, the Mobile Edge Computing that minimizes network latency in the mobile network requires a change in the traditional system architecture that was composed of the existing smart device and high availability server system. However, even with 5G and MEC, since there is a limit to overcome the mobile network state fluctuations only by enhancing the network infrastructure, this study proposes a high-definition video streaming system in ultra-low latency based on the SRT protocol that provides Forward Error Correction and Fast Retransmission. The proposed system shows how to deploy software components that are developed in consideration of the nature of 5G and MEC to achieve sub-1 second latency for 4K real-time video streaming. In the last of this paper, we analyze the most significant factor in the entire video transmission process to achieve the lowest possible latency.

• Journal of the Korea Society of Computer and Information
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• v.19 no.3
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• pp.63-71
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• 2014

We analyze the execution time of Reed-Solomon coding, which is the MAC-layer forward error correction scheme used in CDMA2000 1xEV-DO broadcast services, under different air channel conditions. The results show that the time constraints of MPEG-4 cannot be guaranteed by Reed-Solomon decoding when the packet loss rate (PLR) is high, due to its long computation time on current hardware. To alleviate this problem, we propose three error control schemes. Our static scheme bypasses Reed-Solomon decoding at the mobile node to satisfy the MPEG-4 time constraint when the PLR exceeds a given boundary. Second, dynamic scheme corrects errors in a best-effort manner within the time constraint, instead of giving up altogether when the PLR is high; this achieves a further quality improvement. The third, video-aware dynamic scheme fixes errors in a similar way to the dynamic scheme, but in a priority-driven manner which makes the video appear smoother. Extensive simulation results show the effectiveness of our schemes compared to the original FEC scheme.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.