• 한국철도학회:학술대회논문집
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• 한국철도학회 2007년도 춘계학술대회 논문집
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• pp.1000-1007
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• 2007

Recently, many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased assurance for such applications. Earlier error of overlooked requirement specification can be detected using formal specification method. Also the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In the comparison of other formal specification methods, we choose the Z formal language for applying to the train control system. Using Z is able to realize higher correctness in the requirement specification, and we propose the Statemate of the best solution in formal verification tools for the system modeling and verification. The Statemate makes it possible to prove thoroughly the system execution from the simple graphical modeling of the complicated train control system. Then we can expect that the model-based formal method combining Z with Statemate will be utilized widely for the railway systems due to various strong points.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제12권2호
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• pp.141-148
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• 2006

본 논문에서는 정형 검증 도구를 이용한 보안 소프트웨어의 보안성을 검증하고 검증된 결과를 이용하여 안전한 보안 소프트웨어 개발 방안을 살펴본다. 정형 검증 기법에 따라 사용되어질 수 있는 각 정형 검증 도구들을 살펴보고 그 특성을 파악하여 보안 소프트웨어의 안정성과 신뢰성을 보장하는 적합한 도구들을 알아보고, 보안 소프트웨어 개발 방안을 제시한다. Z 언어를 이용하는 도구인 Z/EVES는 Z명세에 대한 분석 방법을 제시함으로써 보안 소프트웨어에서 가장 많이 사용되는 대표적인 정형 검증 도구이다. 본 논문에서는 보안 소프트웨어 검증을 위하여 C 언어로 작성된 보안 소프트웨어를 Z명세 언어로 변환하고 이것을 Z/EVES도구를 이용한다.

• Journal of Electrical Engineering and Technology
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• 제4권1호
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• pp.87-92
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• 2009

Many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased assurance for such applications. Earlier errors of overlooked requirement specification can be detected using the formal specification method. Also, the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In this paper, we proposed an eclectic approach to incorporate Z(Zed) formal language and 'Statemate MAGNUM', formal method tools using Statechart. Also we applied the proposed method to train control systems for the formal requirement specification and analyzed the specification results.

• 대한안전경영과학회지
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• 제17권1호
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• pp.179-192
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• 2015

In an automated industry PLC plays a central role to control the automation system. Therefore, fault free operation of PLC controlled automation system is essential in order to maximize a firm's productivity. A prior test of control system is a practical way to check fault operations, but it is a time consuming job and can not check all possible fault operation. A formal verification of PLC program could be a best way to check all possible fault situation. Tracing the history of the study on formal verification, we found three problems, the first is that a formal representation of PLC control system is incomplete, the second is a state explosion problem and the third is that the verification result is difficult to use for the correction of control program. In this paper, we propose a transformation method to reproduce the control system correctly in formal model and efficient procedure to verify and correct the control program using verification result. To demonstrate the proposed method, we provided a suitable case study of an automation system.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제8권1호
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• pp.46-61
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• 2002

소프트웨어의 개발 단계 중 품질을 결정하는 주요 단계는 요구 명세 단계로 알려져 있다. 따라서, 소프트웨어 개발 업체는 소프트웨어 요구명세서의 분석을 가장 중요한 단계 중 하나로 취급하고 있고, 특히 안전성이 중요한 시스템의 경우에는 시스템을 운영하기 위하여 국내와 국제적인 규제 기관에서는 요구 명세의 분석을 통한 안전성의 입증을 요구한다. 소프트웨어의 요구 명세 분석을 위한 방법 중 인스펙션과 정형 검증이 가장 효과적인 방법으로 알려져 있다. 본 논문에서는 SCR-style의 요구 명세를 정리 증명기인 PVS를 이용하여 정형 검증을 수행하는 방법을 제안하였다. 그리고, 논문에서 제안된 방법으로 실제 월성 원자력 발전소의 정지 시스템의 검증을 수행하였다. 이 시스템은 인스펙션으로 검증된 적은 있으나 정형 검증 방법으로는 증명된 적이 없고, 국내에서 실제 운영되는 산업계시스템에 정형 검증 방법이 적용된 사례는 매우 드물기 때문에 차후 정형 검증 방법을 적용하기 위한 평가로서도 이와 같은 실험적인 적용이 매우 중요하다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.939-942
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• 2003

Design verification problem is emerging as an important issue to detect any design errors at the early stage of the design. Conventionally, design verifications have been done using a simulation technique. However, this technique has been proved not to cover all potential design errors. Therefore, formal technique is often used to verify digital circuits as an alternative. In this paper we adopted formal verification technique and verified some important properties derived from our pipelined digital systems, using SMV (Symbolic Model Verifier). Our example shows that model checking method (one of formal verification techniques) can be effectively performed in verifying the large digital systems.

• 전기학회논문지P
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• 제57권2호
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• pp.65-71
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• 2008

Recently, many critical control systems are developed using formal methods. When software applied to such systems is developed, the employment of formal methods in the software requirements specification and verification will provide increased. assurance for such applications. Earlier error of overlooked requirement specification can be detected using formal specification method. Also the testing and full verification to examine all reachable states using model checking to undertake formal verification are able to be completed. In this paper, we propose an eclectic approach to incorporate Z(Zed) formal language and 'Statemate MAGNUM' which is formal method tools using Statechart for applying to the railway signaling systems.

• 한국컴퓨터정보학회논문지
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• 제12권6호
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• pp.123-130
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• 2007

본 논문은 객체모델에서 표현되는 객체와 관련성을 형식명세의 상태와 오퍼레이션 도메인으로의 변환 규칙을 제시하였다. 즉 정보모델의 요소인 객체와 관련성을 형식명세 표현에서 상태영역으로 변환하였다. 동적모델의 상태, 이벤트, 행위를 오퍼레이션 영역으로 변환하였다. 비형식적인 객체모델을 형식 명세 언어로 변환하므로써 객체모델을 정형화된 방법으로 검증할 수 있다. 검증과정을 통해 소프트웨어 개말 초기단계에서 모델링 과정의 편리함과 신뢰성을 제공할 수 있다 또한 검증된 모델과 사용자 요구사항 사이의 일관성을 위해 시뮬레이션 도구를 구현하였다. 시뮬레이션 도구는 적합한 모델의 선택과 검증이 가능하도록 하므로 소프트웨어 개발비용과 노력, 개발 시간을 최소화할 수 있다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.358-362
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• 2004

Verification and testing are complementary techniques that are used to increase the level of confidence in the correct functioning of communication systems as prescribed by their specifications. This paper presents an experience of model checking for a formal railway signaling protocol specified in LTS (Labeled Transition System). This formal approach checks deadlock, livelock and reachability for the state and action to verify whether properties expressed in modal logic are true on specifications. We also propose a formal method for semi-automated test case generation for a railway signaling protocol described in I/O FSM (Input/Output Finite State Machine). This enables the generation of more complete and consistent test sequence for conformance testing. The above functions are implemented by C++ language and included within RSPVTE (Railway Signaling Protocol Verification and Testing Environment).

• 한국철도학회논문집
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• 제7권2호
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• pp.114-119
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• 2004

According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.