• Journal of Computing Science and Engineering
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• v.11 no.1
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• pp.9-23
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• 2017

NuDE 2.0 (Nuclear Development Environment 2.0) is a formal-method-based software development, verification and safety analysis environment for safety-critical digital I&Cs implemented with programmable logic controller (PLC) and field-programmable gate array (FPGA). It simultaneously develops PLC/FPGA software implementations from one requirement/design specification and also helps most of the development, verification, and safety analysis to be performed mechanically and in sequence. The NuDE 2.0 now consists of 25 CASE tools and also includes an in-depth solution for indirect commercial off-the-shelf (COTS) software dedication of new FPGA-based digital I&Cs. We expect that the NuDE 2.0 will be widely used as a means of diversifying software design/implementation and model-based software development methodology.

• Journal of KIISE:Information Networking
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• v.33 no.1
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• pp.1-8
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• 2006

Security protocols have usually been developed using informal design and verification techniques. However, many security protocols thought to be secure was found to be vulnerable later. Thus, the importance of formal specification and verification for analyzing the safely of protocols is increasing. With the rise of mobile communication networks, various mobile security protocols have been proposed. In this paper, we identify the security weakness of the ASK mobile Protocol using formal verification technique. In addition, we propose a new ASK protocol modifying its vulnerability and verify its robustness.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1821-1841
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• 1997

This paper presents an automated protocol conformance test sequence generation based on formal methods for LOTOS specification by using and applying many existing related algorithms and technique, such as the testing framework, Rural Chinese Postman tour concepts. We use the state-transition graphs obtained from LOTOS specifications by means of the CAESAR tool. This tool compiles a specification written in LOTOS into an extended Petri net, from which a transition graph of a event finite-state machine(EvFSM) including data is generated. A new characterizing sequence(CS), called Unique Event sequence(UE sequence) is defined. An UE sequence for a state is a sequence of accepted gate events that is unique for this state. Some experiences about UE sequence, partial UE sequence and signature are also explained. These sequences are combined with the concept of the Rural Chinese Postman Tour to obtain an optimal test sequence which is a minimum cost tour of the reference transition graph of the EvFSM. This paper also presents a fault coverage estimation experience of an automated method for optimized test sequences generation and the translation of the test sequence obtained by using our tool to TTCN notation are also given. A prototype of the proposed framework has been built with special attention to real application in order to generated the executable test cases in an automatic way. This formal method on conformance testing can be applied to the protocols related to IN, PCS and ATM for the purpose of verifying the correctness of implementation with respect to the given specification.

• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.995-1004
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• 1998

This paper presents an implementation of model checking tool for LTS process specification, which checks deadlock, livelock and reachability for the state and action. The implemented formal checker using modal mu-calculus is able to verify whether properties expressed in modal logic are true on specifications. We prove experimentally that it is powerful to check, safety and liveness for the state and action on LTS. The tool is implemented by $C^{++}$ language and runs on IBM PC under Windows NT.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.28-37
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• 1996

Syntax notation one (ASN.1) defined by ITU-T and ISO, is a formal abstrct specification language which has been widely used in international standards specifiation to inteconnect distributed open systems. It si necessary to have well defined encoder/decoder modules which taranslate ASN.1 datum to BER octets stream to interconnect distributed open systems. In this paper, we designed and implemented a new ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which atutomatically translates and ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which automatically translates an ASN.1 specification into C-language BER encoders and decoders with simple and neat I/F for the defined ASN.1 data types, and enhanced BER (basic encoding rules)encoding/decoding libraries, called HY(hanyang)BER library, and useful utility functions. And this paper discusses HYASNC compiler, HY BER runtime library's design and implementation principles, and also evaluates the perfomrance of HY BER library and the interoperability with other ASN.1 compilers.

• Proceedings of the Korea Society for Simulation Conference
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• 1999.10a
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• pp.41-45
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• 1999

본 논문에서는 소프트웨어 시스템의 설계 및 구현 과정에서 있을 수 있는 설계 변경 및 이에 따른 다른 변경 요인들을 정확하게 파악하고, 구현상의 변경으로 인한 전체 시스템이 영향 등을 체계적으로 정립하는 소프트웨어 설계 방법론을 특정 공정의 사용자 인터페이스 시스템을 통해 제시하였다. 대상 시스템, 즉 인터페이스 시스템을 시스템 이론(System theory)에서 정의하는 구조적 입출력 시스템 레벨(Structural I/O System level)의 요소들로 표현하고 다시 구조적 입출력 시스템 레벨을 입출력 시스템 레벨(I/O System level)로 변환하였다. 이를 다시 DEVS 모델로 재구성하여 DEVS(Discrete EVent system Specification) 시뮬레이션 환경에서 제공하는 시뮬레이터를 통하여 대상 시스템의 중요한 동적 특성을 소프트웨어 초기설계 시 또는 설계 변경 후 미리 파악할 수 있도록 하였다.

• Proceedings of the KSR Conference
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• 2003.10c
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• pp.581-586
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• 2003

As a very important part in development of the protocol, verification and conformance test for protocol specification are complementary techniques that are used to increase the level of confidence in the system functions. as prescribed by their specifications. In this paper, we verify the safety and liveness properties of rail signal control protocol type 1 specified in LTS(Labeled Transition System) with model checking method, and experimentally prove that it is possible to check for the deadlock, livelock and rechability of the states and actions on LTS. We also propose a formal method on generation of conformance test cases using the concept of UIO sequences from verified protocol specification.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.05d
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• pp.661-664
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• 2002

컴포넌트를 개발하는데 있어서 컴포넌트 명세의 정확성과 명세의 검증을 통하여 에러를 찾아 낸다는 것은 컴포넌트의 전체 품질에 매우 중요한 의미를 갖는다. 그러나, 기존의 컴포넌트 명세는 구문적인 측면은 잘 정의하고 있지만, 의미적인 측면은 자연어를 사용하여 모순과 모호성이 흔히 발생한다. 컴포넌트 명세에 있어서 정형적 문법을 사용할 경우 이러한 모호성을 제거함으로써 명세 오류들을 매우 효과적으로 줄여준다. 본 논문에서는 컴포넌트의 품질을 높일 수 있도록 분석력과 논리성이 검증된 정형 명세 언어 Z의 스키마 확장을 이용하여 컴포넌트를 명세하므로써 컴포넌트 구현 및 사용상의 오류를 분석할 수 있는 방법을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11c
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• pp.2115-2118
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• 2002

이 논문에서는 정형적 명세를 이용하여 테스트 데이터를 추출하는 방법을 제안한다. 복잡하고 구성요소가 다양한 웹 프로그램의 기능을 Object-Z 정형 명세 언어를 이용하여 핵심적으로 나타낸다. 이로부터 상태 모델을 구성하고 최상위 레벨의 STD 에서 세부적으로 STD 를 추가하여 테스트 시나리오를 추출한다. 실험 대상은 웹 뱅킹 업무로 정하고 계좌개설 과정의 테스트 데이터를 추출하였다. 제안한 방법은 사용기반 테스트 기법과 결합하여 웹 소프트웨어의 테스트 자동화에 중요한 요소가 될 것이다.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.920-923
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• 2002

In this paper, we propose Class Diagram With Constraints (CDWC) as an object oriented modeling technique which makes validation possible in software development. CDWC is a simple and basic model for the object oriented analysis, and has a reasonable strictness for software developers. CDWC consists of class diagrams and constraints (invariant and pre/post conditions), using UML and a subset of OCL.. We introduce a method of validation of CDWC using the verification technique of algebraic formal specification language CafeOBJ.