• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 춘계학술대회 논문집
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• pp.641-642
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• 2009

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.925-926
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.531-532
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.461-462
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• 2011

• Journal of Welding and Joining
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• 제30권6호
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• pp.113-119
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• 2012

Ultrasonic bonding is the novel packaging method for flip-chip with high yield and low-temperature bonding. The bonding module is a core part of the bonding machine, which can transfer the ultrasonic energy into the bonding spot. In this paper, we propose topology optimization technique which can make new design of boding modules due to the constraints on resonance frequency and mode shapes. The designed bonding module using topology optimization was fabricated in order to evaluate the bonding performance and reliable operation during the continuous bonding process. The actual production models based on the proposed design satisfied the target frequency range and ultrasonic power. The bonding test was performed using flip-chip with lead-free Sn-based bumps, the results confirmed that the bonding strength was sufficient with the designed bonding modules. Also the performance degradation of the bonding module was not observed after the 300-hour continuous process with bonding conditions.

• Journal of Welding and Joining
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• 제22권6호
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• pp.36-42
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• 2004

Experimental and numerical approaches on the thermal fatigue for the solder joint of flip chip package are discussed. However, it is one of the most difficult problems to choose the proper fatigue model. It was found that viscoplstic FE model with Darveaux method was very desirable and useful to predict the thermal fatigue life of solder joint for flip chip package under $208{\~}423K$ thermal cycling condition such as steep slope of temperature(JEDEC standard condition C). Thermal fatigue life was 1075 cycles as a result of viscoplatic model. It was a good agreement compared to the experimental. And also, it was found from the experimental that probability of the thermal fatigue life was $60{\%}$ at 1500 cycles.

• 마이크로전자및패키징학회지
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• 제14권1호
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• pp.19-26
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• 2007

본 연구의 목적은 CMOS 이미지 센서용 Au 플립칩 범프와 전해 도금된 Au 기판 사이의 초음파 접합의 가능성 연구이다. 초음파 접합 조건을 최적화하기 위해서, 대기압 플라즈마 세정 후 접합 압력과 시간을 달리하여 초음파 접합 후 전단 시험을 실시하였다. 범프의 접합 강도는 접합 압력과 시간 변수에 크게 좌우되었다. Au 플립칩 범프는 상온에서 성공적으로 하부 Au 도금 기판과 접합되었으며, 최적 조건 하에서 접합 강도는 약 73 MPa이었다.

• 전자공학회논문지A
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• 제33A권3호
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• pp.140-151
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• 1996

In this paper, we analyze the variations of thermal characteristics of LD (laser diode) arrays packaged by a flip-chip bonding method. When we simulate the temperature distribution in LD arrays with a BEM (boundary element method) program coded in this paper, we find that thermal crosstalks in LD arrays packaged by the flip-chip bonding method increases by 250-340% compared to that in LD arrays packaged by previous methods. In the LD array module packaged by the flip-chip bonding technique without TEC (thermo-electric cooler), the important parameter is the absolute temperature of the active layer increased due cooler), the important parameter is the absolute temperature of th eactiv elayers of LD arrays to thermal crosstalk. And we find that the temperature of the active layers of LD arrays increases up to 125$^{\circ}C$ whenall four LDs, without a carefully designed heatsink, are turned on, assuming the power consumption of 100mW from each LD. In order to reduce thermal crosstalk we propose a heatsink sturcture which can decrease the temeprature at the active layer by 40%.

• 한국생산제조학회지
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• 제21권2호
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• pp.225-231
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• 2012

Drop simulations of the board level in the flip chips with solder joints have been highlighted for years, recently. Also, through the study on the life prediction of thermal fatigue in the flip chips considering underfill, its importance has been issued greatly. In this paper, dynamic analysis using the implicit method in the Finite Element Analysis (FEA) is carried out to assess the factors effecting on flip chips considering underfill. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard is modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. Modal analysis is simulated to find out the relation between drop impact and vibration of the board system.

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.49-56
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• 2012

최근 전자 제품의 소형화, 박형화 및 집적화에 따라 칩과 기판을 연결하는 범프의 미세화가 요구되고 있다. 그러나 범프의 미세화는 직경 감소와 UBM의 단면적 감소로 인하여 전류 밀도를 증가시켜 전기적 단락을 야기할 수 있다. 특히 범프에서 형성되는 금속간화합물과 KV의 형성은 전기적 및 기계적 특성에 큰 영향을 줄 수 있다. 따라서 본 논문에서는 유한요소해석을 이용하여 플립칩 범프의 열변형을 분석하였다. 우선 TCT의 온도조건을 통하여 플립칩 패키지의 열변형 특성을 분석한 결과, 범프의 열 변형이 시스템의 구동에 큰 영향을 미칠 수 있음을 확인하였다. 그리고 범프의 열변형 특성에 큰 영향을 미칠 것을 생각되는 IMC층의 두께와 범프의 직경을 변수로 선정하여 온도변화, 열응력 및 열변형에 대한 해석을 수행하였으며, 이를 통하여 IMC층이 범프에 영향을 미치는 원인에 대한 분석을 수행하였다.