• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.10
• /
• pp.65-70
• /
• 2008

We design and fabricate the 94 GHz Coplanar waveguide(CPW)-to-rectangular waveguide transition that is transmits signal smoothly between the CPW, which is a popular transmission line of the planar circuits, and rectangular waveguide for the 94 GHz transceiver system. The proposed transition composed of the unilateral fin-line taper and open type CPW-to-slot-line transition is based on the hard and inflexible sapphire for the flip-chip bonding of the planar MMICs using conventional MMIC technology. We optimize a single section transition to achieve low loss by using an EM field solver of Ansoft's HFSS and fabricate the back- to-back transition that is measured by Anritsu ME7808A Vector Network Analyzer in a frequency range of $85{\sim}105$ GHz. From the measurement and do-embedding CPW with 3 mm length, an insertion and return loss of a single-section transition are 1.7 dB and more an 25 than at 94 GHz, respectively.

• Journal of the Microelectronics and Packaging Society
• /
• v.11 no.3 s.32
• /
• pp.37-45
• /
• 2004

Electroless Ni(P) has been widely used for under bump metallization (UBM) of flip chip and surface finish layer in microelectronic packaging because of its excellent solderability, corrosion resistance, uniformity, selective deposition without photo-lithography, and also good diffusion barrier. However, the brittle fracture at solder joints and the spatting of intermetallic compound (IMC) associated with electroless Ni(P) are critical issues for its successful applications. In the present study, the mechanism of IMC spatting and microstructure change of the Ni(P) film were investigated with varying P content in the Ni(P) film (4.6,9, and $13 wt.\%$P). A reaction between Sn penetrated through the channels among $Ni_3Sn_4$ IMCs and the P-rich layer ($Ni_3P$) of the Ni(P) film formed a $Ni_3SnP$ layer. Thickening of the $Ni_3SnP$ layer led to $Ni_3Sn_4$ spatting. After $Ni_3Sn_4$ spatting, the Ni(P) film directly contacted the molten solder and the $Ni_3P$ phase further transformed into a $Ni_2P$ phase. During the crystallization process, some cracks formed in the Ni(P) film to release tensile stress accumulated from volume shrinkage of the film.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.4
• /
• pp.23-29
• /
• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.34 no.2
• /
• pp.245-253
• /
• 2010

The reliability problems of flip chip packages subjected to temperature change during the packaging process mainly occur due to mismatches in the coefficients of thermal expansion as well as features with time-dependent material properties. Resin molding compounds like glass fiber reinforced epoxy composites used as the dielectric layer in printed circuit boards (PCB) strongly exhibit viscoelastic behavior, which causes their Young's moduli to not only be temperature-dependent but also time-dependent. In this study, the stress relaxation and creep tests were used to characterize the viscoelastic properties of the glass fiber reinforced epoxy composite. Using the viscoelastic properties, finite element analysis (FEA) was employed to simulate thermal loading in the pre-baking process and predict thermal warpage. Furthermore, the effect of viscoelastic features for the major polymeric material on the dielectric layer in the PCB (the glass fiber reinforced epoxy composite) was investigated using FEA.

• Journal of the Microelectronics and Packaging Society
• /
• v.13 no.1 s.38
• /
• pp.23-29
• /
• 2006

Ultrasonic soldering of Si-wafer to FR-4 PCB at ambient temperature was investigated. The UBM of Si-substrate was Cu/ Ni/ Al from top to bottom with thickness of $0.4{\mu}m,\;0.4{\mu}m$, and $0.3{\mu}m$ respectively. The pad on FR-4 PCB comprised of Au/ Ni/ Cu from top to bottom with thickness of $0.05{\mu}m,\;5{\mu}m$, and $18{\mu}m$ respectively. Sn-3.5wt%Ag foil rolled to $100{\mu}m$ was used for solder. The ultrasonic soldering time was varied from 0.5 s to 3.0 s and the ultrasonic power was 1,400 W. The experimental results show that a reliable bond by ultrasonic soldering at ambient temperature was obtained. The shear strength increased with soldering time up to a maximum of 65 N at 2.5 s. The strength decreased to 34 N at 3.0 s because cracks were generated along the intermetallic compound between Si-wafer and Sn-3.5wt%Ag solder. The Intermetallic compound produced by ultrasonic soldering between the Si-wafer and the solder was $(Cu,Ni)_{6}Sn_{5}$.

• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.4
• /
• pp.11-15
• /
• 2001

In this paper, hermetic sealing technology was studied for wafer level packaging of the RF-MEMS devices. With the flip-chip bonding method. this non-conductive B-stage epoxy sealing will be profit to the MEMS device sealing. It will be particularly profit to the RF-MEMS device sealing. B-stage epoxy can be cured by 2-step and hermetic sealing can be obtained. After defining 500 $\mu\textrm{m}$-width seal-lines on the glass cap substrate by screen printing, it was pre-baked at $90^{\circ}C$ for about 30 minutes. It was, then, aligned and bonded with device substrate followed by post-baked at $175^{\circ}C$ for about 30 minutes. By using this 2-step baking characteristic, the width and the height of the seal-line could be maintained during the sealing process. The height of the seal-line was controlled within $\pm$0.6 $\mu\textrm{m}$ in the 4 inches wafer and the bonding strength was measured to about 20MPa by pull test. The leak rate, that is sealing characteristic of the B-stage epoxy, was about $10^{-7}$ cc/sec from the leak test.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.1
• /
• pp.75-82
• /
• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2012.11a
• /
• pp.123-123
• /
• 2012

최근 연구되고 있는 TSV(Through Silicon Via) 기술은 Si 웨이퍼 상에 직접 전기적 연결 통로인 관통홀을 형성하는 방법으로 칩간 연결거리를 최소화 할 수 있으며, 부피의 감소, 연결부 단축에 따른 빠른 신호 전달을 가능하게 한다. 이러한 TSV 기술은 최근의 초경량화와 고집적화로 대표되는 전자제품의 요구를 만족시킬 수 있는 차세대 실장법으로 기대를 모으고 있다. 한편, 납땜 재료의 주 원료인 주석은 주로 반도체 소자의 제조, 반도체 칩과 기판의 접합 및 플립 칩 (Flip Chip) 제조시의 범프 형성 등 반도체용 배선재료에 널리 사용되고 있다. 최근에는 납의 유해성 때문에 대부분의 전자제품은 무연솔더를 이용하여 제조되고 있지만, 주석을 이용한 반도체 소자가 고밀도화, 고 용량화 및 미세피치(Fine Pitch)화 되고 있기 때문에, 반도체 칩의 근방에 배치된 주석으로부터 많은 알파 방사선이 방출되어 메모리 셀의 정보를 유실시키는 소프트 에러 (Soft Error)가 발생되는 위험이 많아지고 있다. 이로 인해, 반도체 소자 및 납땜 재료의 주 원료인 주석의 고순도화가 요구되고 있으며, 특히 알파 방사선의 방출이 낮은 로우알파솔더 (Low Alpha Solder)가 요구되고 있다. 이에 따라 본 연구는 4인치 실리콘 웨이퍼상에 직경 $60{\mu}m$, 깊이 $120{\mu}m$의 비아홀을 형성하고, 비아 홀 내에 기능 박막증착 및 전해도금을 이용하여 전도성 물질인 Cu를 충전한 후 직경 $80{\mu}m$의 로우알파 Sn-1.0Ag-0.5Cu 솔더를 접합 한 후, 접합부 신뢰성 평가를 수행을 위해 고속 전단시험을 실시하였다. 비아 홀 내 미세구조와 범프의 형상 및 전단시험 후 파괴모드의 분석은 FE-SEM (Field Emission Scanning Electron Microscope)을 이용하여 관찰하였다. 연구 결과 비아의 입구 막힘이나 보이드(Void)와 같은 결함 없이 Cu를 충전하였으며, 고속전단의 경우는 전단 속도가 증가할수록 취성파괴가 증가하는 경향을 보였다. 본 연구를 통하여 전해도금을 이용한 비아 홀 내 Cu의 고속 충전 및 로우알파 솔더 볼의 범프 형성이 가능하였으며, 이로 인한 전자제품의 소프트에러의 감소가 기대된다.

• Korean Journal of Optics and Photonics
• /
• v.8 no.6
• /
• pp.510-515
• /
• 1997

Packaging takes an extremely important element of optical module cost due primarily to the added complication of alignment between semiconductor devices and optical fiber, and many efforts have been devoted on reducing the cost by eliminating the complicated optical alignment procedures in passive manner. In this study, we fabricated silicon optical benches on which the optical alignments are accomplished passively. To improve the positioning accuracy of a flip-chip bonded LD, we adopted fiducial marks and solder dams which are self-aligned with V-groove etch patterns, and a stand-off to control the height and to improve the heat dissipation of LD. Optical sub-assemblies exhibited an average efficiency of -11.75$\pm$1.75 dB(1$\sigma$) from the LD-to-single mode fiber coupling and an average sensitivity of -35.0$\pm$1.5 dBm from the fiber and photodetector coupling.

• Korean Journal of Materials Research
• /
• v.12 no.9
• /
• pp.750-760
• /
• 2002

In this study, three solders, Sn-37Pb, Sn-3.5Ag, and Sn-3.8Ag-0.7Cu were screen printed on both electroless Ni/Au and OSP metal finished micro-via PCBs (Printed Circuit Boards). The interfacial reaction between PCB metal pad finish materials and solder materials, and its effects on the solder bump joint mechanical reliability were investigated. The lead free solders formed a large amount of intermetallic compounds (IMC) than Sn-37Pb on both electroless Ni/Au and OSP (Organic Solderabilty Preservatives) finished PCBs during solder reflows because of the higher Sn content and higher reflow temperature. For OSP finish, scallop-like $Cu_{6}$ /$Sn_{5}$ and planar $Cu_3$Sn intermetallic compounds (IMC) were formed, and fracture occurred 100% within the solder regardless of reflow numbers and solder materials. Bump shear strength of lead free solders showed higher value than that of Sn-37Pb solder, because lead free solders are usually harder than eutectic Sn-37Pb solder. For Ni/Au finish, polygonal shaped $Ni_3$$Sn_4$ IMC and P-rich Ni layer were formed, and a brittle fracture at the Ni-Sn IMC layer or the interface between Ni-Sn intermetallic and P-rich Ni layer was observed after several reflows. Therefore, bump shear strength values of the Ni/Au finish are relatively lower than those of OSP finish. Especially, spalled IMCs at Sn-3.5Ag interface was observed after several reflow times. And, for the Sn-3.8Ag-0.7Cu solder case, the ternary Sn-Ni-Cu IMCs were observed. As a result, it was found that OSP finished PCB was a better choice for solders on PCB in terms of flip chip mechanical reliability.