• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.65-70
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• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.

• Journal of Welding and Joining
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• v.19 no.5
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• pp.520-525
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• 2001

The Sn-Pb eutectic solder bump formation ($150\mu\textrm{m}$ diameter, $250\mu\textrm{m}$ pitch) by electroplating was studied for flip chip package fabrication. The effect of current density and plating time on Sn-Pb deposit was investigated. The morphology and composition of plated solder surface was examined by scanning electron microscopy. The plating thickness increased wish increasing time. The plating rate became constant at limiting current density. After the characteristics of Sn-Pb plating were investigated, Sn-Pb solder bumps were fabricated in optimal condition of $7A/dm^$. 4hr. Ball shear test after reflow was performed to measure adhesion strength between solder bump and UBM (Under Bump Metallurgy). The shear strength of Sn-Pb bump after reflow was higher than that of before reflow.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.2
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• pp.27-31
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• 2003

RF characteristics of CPW(coplanar waveguide) pattern with bonding pads used in flip-chip packaging of GaAs is studied in the frequency range of 1 GHz to 35 GHz. Simulation, fabrication and evaluation are performed for the proposed patterns. Measurement results show proposed patterns have similar properties of $S_{11}$below -31 dB and $S_{21}$ above -0.19 dB with typical CPW In addition RF properties are improved with the increase of width of ground line. This indicates CPW structure with bonding pads keeps RF characteristics of typical CPW.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.2
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• pp.193-201
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• 2011

Recently, mechanical reliabilities including a drop test have been a hot issue. In this paper, solder balls with new components which are Sn-3.0Ag-0.5Cu and Sn-1.0Ag-0.5Cu-0.05N are introduced, and board level drop test for them are conducted under JEDEC standard in which the board with 15 flip chips is dropped as 1,500g acceleration during 0.5ms. The drop simulations are studied by using a implicit method in the ANSYS LS-DYNA, and modal analysis is made. Through both analyses, the solder balls with new components are evaluated under the drop. It is found that the maximum stress of each chip is occurred between the solder ball and the PCB, and the highest value among the maximum stresses in the chips is occurred on the chip nearest to fixed holes on the board in the drop tests and simulations.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.10 s.253
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• pp.957-965
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• 2006

A high-performance hot chuck is designed as a heating device for an ultra-precision flip-chip bonder with infrared alignment system. Analysis of design requirements for thermal performance leads to a radiative heating mechanism employing two halogen lamps as heating source. The heating tool is made of silicon carbide characterized by high thermal diffusivity and small thermal expansion coefficient. Experimental tests are performed to assess heat-up performance and temperature uniformity of the heating tool. It is revealed that the initial design of hot chuck results in a good heat-up speed but there exist a couple of troubles associated with control and integrity of the device. As a means to resolve the raised issues, a revised version of heating tool is proposed, which consists of a working plate made of silicon carbide and a supporting structure made of stainless steel. The advantages of this two-body heating tool are discussed and the improved features are verified experimentally.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.415-416
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• 2008

The finite element model was used to simulate the temperature distribution of a arrayed vertical-cavity surface-emitting laser (VCSEL). In this work, the dimension of AlGaAs/GaAs based VCSEL array was $50{\mu}m$ active diameter and $250{\mu}m$ pitch, and AuSn solder of 80wt%Au-20wt%Sn was included to flip-chip bond. The results of the thermal simulation will be applied to predict the thermal cross-talk in high speed parallel optical interconnects.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.127-130
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• 2003

An RSFQ (Rapid Single Flux Quantum) counter can be used as a frequency divider that was an essential part of a programmable voltage standard chip. The voltage standard chip is composed of two circuit parts, a counter and an antenna Analog signal of tens to hundreds ㎓ may be applied to a finline antenna part. This analog signal can be converted to the stream of SFQ voltage pulses by a DC/SFQ circuit. The number of voltage pulses can be reduced by 2n times when they pass through a counter that is composed of n T Flip-Flops (Toggle Flip-Flop). Such a counter can be used not only as a frequency divider, but also to build a programmable voltage standard chip. So, its application range can be telecommunication, high speed RAM, microprocessor, etc. In this work, we have used Xic, WRspice, and L-meter to design an RSFQ counter. After circuit optimization, we could obtain the bias current margins of the T Flip-Flop circuit to be above 31％ Our RSFQ counter circuit designs were based on the 1 ㎄/$\textrm{cm}^2$ niobium trilayer technology.

• Korean Journal of Metals and Materials
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• v.46 no.5
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• pp.310-314
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• 2008

Electromigration test of flip chip solder bump is performed at $140^{\circ}C$ C and $4.6{\times}10^4A/cm^2$ conditions in order to compare electromigration with thermomigration behaviors by using electroplated Sn-3.5Ag solder bump with Cu under-bump-metallurgy. As a result of measuring resistance with stressing time, failure mechanism of solder bump was evaluated to have four steps by the fail time. Discrete steps of resistance change during electromigration test are directly compared with microstructural evolution of cross-sectioned solder bump at each step. Thermal gradient in solder bump is very high and the contribution of thermomigration to atomic flux is comparable with pure electromigration effect.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.138-140
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• 2001

Fluxless flip chip bonding using plasma & ultrasonic wave was investigated in order to evaluate the effect of plasma & ultrasonic treatment on the bondability of the Sn-3.5wt%Ag solder bumped die to TSM-coated glass substrate. The $Ar+10%H_2plasma$ was effective in removing tin oxide on solder surface. The die shear strength of the plasma-treated Si-chip is higher than that of non-treated specimen but lower than that of specimen bonded with flux. The die shear strength with the bonding load at 25W ultrasonic power increased to 0.8N/bump for all bonding temperature but decreased above 1.0N/bump.

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.456-462
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• 2002

In the present work, a low cost and fine pitch bumping process by electroless Ni/immersion Au UBM (under bump metallurgy) and stencil printing for the solder bump on the Al pad is discussed. The Chip used this experimental had an array of pad 14x14 and zincate catalyst treatment is applied as the pretreatment of Al bond pad, it was shown that the second zincating process produced a dense continuous zincating layer compared to first zincating. Ni UBM was analyzed using Scanning electron microscopy, Energy dispersive x-ray, Atomic force microscopy, and X-ray diffractometer. The electroless Ni-P had amorphous structures in as-plated condition. and crystallized at 321 C to Ni and Ni$_3$P. Solder bumps are formed on without bridge or missing bump by stencil print solder bump process.