• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.5
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• pp.887-892
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• 2019

In this study, after 20nm-thick $SiO_2$ thin film was deposited by PECVD method on the PES substrate, which is known to have the highest heat resistance among plastic substrates, as a buffer layer, ITZO thin films were deposited by RF magnetron sputtering method to investigate the electrical and optical properties according to the working pressure. The ITZO thin film deposited at the working pressure of 3mTorr showed the best electrical properties with a resistivity of $8.02{\times}10^{-4}{\Omega}-cm$ and a sheet resistance of $50.13{\Omega}/sq.$. The average transmittance in the visible region (400-800nm) of all ITZO films was over 80% regardless of working pressure. The Figure of merit showed the largest value of $23.90{\times}10^{-4}{\Omega}^{-1}$ in the ITZO thin film deposited at 3mTorr. This study found that ITZO thin films are very promising materials to replace ITO thin films in next-generation flexible display devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.222-222
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• 2012

Metal oxide gas sensors based on semiconductor type have attracted a great deal of attention due to their low cost, flexible production and simple usability. However, most works have been focused on n-type oxides, while the characteristics of p-type oxide gas sensors have been barely studied. An investigation on p-type oxides is very important in that the use of them makes possible the novel sensors such as p-n diode and tandem devices. Monoclinic cupric oxide (CuO) is p-type semiconductor with narrow band gap (~1.2 eV). This is composed of abundant, nontoxic elements on earth, and thus low-cost, environment-friendly devices can be realized. However, gas sensing properties of neat CuO were rarely explored and the mechanism still remains unclear. In this work, the neat CuO layers with highly ordered mesoporous structures were prepared by a template-free, one-pot solution-based method using novel ink solutions, formulated with copper formate tetrahydrate, hexylamine and ethyl cellulose. The shear viscosity of the formulated solutions was 5.79 Pa s at a shear rate of 1 s-1. The solutions were coated on SiO2/Si substrates by spin-coating (ink) and calcined for 1 h at the temperature of $200{\sim}600^{\circ}C$ in air. The surface and cross-sectional morphologies of the formed CuO layers were observed by a focused ion beam scanning electron microscopy (FIB-SEM) and porosity was determined by image analysis using simple computer-programming. XRD analysis showed phase evolutions of the layers, depending on the calcination temperature, and thermal decompositions of the neat precursor and the formulated ink were investigated by TGA and DSC. As a result, the formation of the porous structures was attributed to the vaporization of ethyl cellulose contained in the solutions. Mesoporous CuO, formed with the ink solution, consisted of grains and pores with nano-meter size. All of them were strongly dependent on calcination temperature. Sensing properties toward H2 and C2H5OH gases were examined as a function of operating temperature. High and fast responses toward H2 and C2H5OH gases were discussed in terms of crystallinity, nonstoichiometry and morphological factors such as porosity, grain size and surface-to-volume ratio. To our knowledge, the responses toward H2 and C2H5OH gases of these CuO gas sensors are comparable to previously reported values.

• Journal of the Korean Vacuum Society
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• v.20 no.5
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• pp.327-332
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• 2011

Plasma polymerized styrene (ppS) thin films were prepared on ITO coated glass substrates for a MIM (metal-insulator-metal) structure with thermally evaporated Au thin film as metal contact. Also the ppS thin films were applied as organic insulator to a MIS (metal-insulatorsemiconductor) device with thermally evaporated pentacene thin film as organic semiconductor layer. After the I-V and C-V measurements with MIM and MIS structures, the ppS revealed relatively higher dielectric constant of k=3.7 than those of the conventional poly styrene and very low leakage current density of $1{\times}10^{-8}Acm^{-2}$ at electric field strength of $1MVcm^{-1}$. The MIS structure with the ppS dielectric layer showed negligible hysteresis in C-V characteristics. It would be therefore expected that the proposed ppS could be applied as a promising dielectric/insulator to organic thin film transistors, organic memory devices, and flexible organic electronic devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.3
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• pp.578-584
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• 2017

$SiO_2$ buffer layer (100 nm) has been deposited on PET substrate by electron beam evaporation. And then, IZTO (In-Zn-Sn-O) thin film has been deposited on $SiO_2$/PET substrate with different RF power of 30 to 60 W, working pressure, 1 to 7 mTorr, by RF magnetron sputtering. Structural, electrical and optical properties of IZTO thin film have been analyzed with various RF powers and working pressures. IZTO thin film deposited on the process condition of 50 W and 3 mTorr exhibited the best characteristics, where figure of merit was $4.53{\times}10^{-3}{\Omega}^{-1}$, resistivity, $4.42{\times}10^{-4}{\Omega}-cm$, sheet resistance, $27.63{\Omega}/sq.$, average transmittance (400-800 nm), 81.24%. As a result of AFM, all the IZTO thin film has no defects such as pinhole and crack, and RMS surface roughness was 1.147 nm. Due to these characteristics, IZTO thin film deposited on $SiO_2$/PET structure was found to be a very compatible material that can be applied to the next generation flexible display device.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.169-169
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• 2010

As display industry requires various applications for future display technology, which can guarantees high level of flexibility and transparency on display panel, oxide semiconductor materials are regarded as one of the best candidates. $InGaZnO_4$(IGZO) has gathered much attention as a post-transition metal oxide used in active layer in thin-film transistor. Due to its high mobility fabricated at low temperature fabrication process, which is proper for application to display backplanes and use in flexible and/or transparent electronics. Electrical performance of amorphous oxide semiconductors depends on the resistance of the interface between source/drain metal contact and active layer. It is also affected by sheet resistance on IGZO thin film. Controlling contact/sheet resistance has been a hot issue for improving electrical properties of AOS(Amorphous oxide semiconductor). To overcome this problem, post-annealing has been introduced. In other words, through post-annealing process, saturation mobility, on/off ratio, drain current of the device all increase. In this research, we studied on the relation between device's resistance and post-annealing temperature. So far as many post-annealing effects have been reported, this research especially analyzed the change of electrical properties by increasing post-annealing temperature. We fabricated 6 main samples. After a-IGZO deposition, Samples were post-annealed in 5 different temperatures; as-deposited, $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$ and $500^{\circ}C$. Metal deposition was done on these samples by using Mo through E-beam evaporation. For analysis, three analysis methods were used; IV-characteristics by probe station, surface roughness by AFM, metal oxidation by FE-SEM. Experimental results say that contact resistance increased because of the metal oxidation on metal contact and rough surface of a-IGZO layer. we can suggest some of the possible solutions to overcome resistance effect for the improvement of TFT electrical performances.

• Journal of Adhesion and Interface
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• v.24 no.2
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• pp.64-68
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• 2023

Organic field-effect transistors (OFETs) are attracting attention in the field of next-generation electronic devices, and they can be fabricated on a flexible substrate using an organic semiconductor as a channel layer. In particular, DPP-based semiconducting conjugated polymers are actively used because they have higher charge carrier mobility than other organic semiconductors, but they are still lower than inorganic semiconductors, so various studies are being conducted to improve the charge carrier mobility. In this study, the charge carrier mobility is improved by controlling the surface energy of the substrate by forming self-assembled monolayers (SAMs). As the surface energy of the substrate is controlled by the SAMs, the crystallinity increases, thereby improving the charge carrier mobility by 14 times from 3.57×10^-3 cm²V^-1s^-1 to 5.12×10^-2 cm²V^-1s^-1

• Journal of Industrial Convergence
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• v.20 no.12
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• pp.79-85
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• 2022

Recently, a smartphone manufactured on a flexible substrate has been released as an electronic device, and research on a stretchable electronic device is in progress. In this paper, a silicon-based stretchable material is made and used as a substrate to implement and evaluate an optical sensor device using oxide semiconductor. To this end, a substrate that stretches well at room temperature was made using a silicone-based solution rubber, and the elongation of 350% of the material was confirmed, and optical properties such as reflectivity, transmittance, and absorbance were measured. Next, since the surface of these materials is hydrophobic, oxygen-based plasma surface treatment was performed to clean the surface and change the surface to hydrophilicity. After depositing an AZO-based oxide film with vacuum equipment, an Ag electrode was formed using a cotton swab or a metal mast to complete the photosensor. The optoelectronic device analyzed the change in current according to the voltage when light was irradiated and when it was not, and the photocurrent caused by light was observed. In addition, the effect of the optical sensor according to the folding was additionally tested using a bending machine. In the future, we plan to intensively study folding (bending) and stretching optical devices by forming stretchable semiconductor materials and electrodes on stretchable substrates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.1-9
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• 2006

In the System-on-Chip(SoC) design, the global wires are critical parts for the performance. Therefore, the global wires need to be pipelined using flip-flops or latches. Since the timing constraint of the latch is more flexible than it of the flip-flop, the latch-based design can provide a better solution for the clock period. Retiming is an optimizing technique which repositions memory elements in the circuits to reduce the clock period. Traditionally, retiming is used on gate-level netlist, but retiming for SoC is used on macro-level netlist. In this paper, we extend the previous work of retiming for SoC using flip-flops to retiming for SoC using single-phase clocked latches. In this paper we propose a MILP for retiming for SoC using single-phase clocked latches, and apply the fixpoint computation to solve it. Experimental results show that retiming for SoC using latches reduces the clock period of circuits by average 10 percent compared with retiming for SoC using flip-flops.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.167-171
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• 2014

While the development of a portable plate panel display, thinning, high color reproduction, high brightness studies have been actively performed. LED, OLED is used as a light source. The research on quantum dot is much accomplished by the material of light source. Such quantum dot is the next generation semiconductor nano fluorescent substance because quantum dot has the high color reproduction and flexible display characteristic. In this study, we presented to method of using the quantum dot for implementation of the plate panel display. Quantum Dot (CdSe/ZnS), having a 100um thickness, is spread in PET barrier film. A Blue LED having a wavelength of 455nm as a light source irradiating light to the optical characteristic of the devices produced and evaluated. Also we presented the possibility for application with the color change film of the LCD.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.