• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.70-82
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• 2014

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.27-31
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• 2006

We reported the grain growth of pentacone on $HfO_2$ film depending on OTS treatment. The hydrophilic $HfO_2$ thin film was changed into hydrophobic with less interface energy by OTS treatment. The grain size of pentacene on OTS/$HfO_2$ film was increased from 50 nm to 90 nm with the variation of surface energy and the structure was maintained 3-dimensional island structure. Pentacene on OTS/$HfO_2$ surface was directionally arrayed due to appearance of the only thin film phase without bulk phase by OTS treatment.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.6
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• pp.588-593
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• 2023

The advantage of OTFT technology is that large-area circuits can be manufactured on flexible substrates using a low-cost solution process such as inkjet printing. Compared to silicon-based inorganic semiconductor processes, the process temperature is lower and the process time is shorter, so it can be widely applied to fields that do not require high electron mobility. Materials that have utility as electrode materials include carbon that can be solution-processed, transparent carbon thin films, and metallic nanoparticles, etc. are being studied. Recently, a technology has been developed to facilitate charge injection by coating the surface of the Al electrode with solution-processable titanium oxide (TiOx), which can greatly improve the performance of OTFT. In order to commercialize OTFT technology, an appropriate method is to use a complementary circuit with excellent reliability and stability. For this, insulators and channel semiconductors using organic materials must have stability in the air. In this study, carbon-doped Mo (MoC) thin films were fabricated with different graphite target power densities via unbalanced magnetron sputtering (UBM). The influence of graphite target power density on the structural, surface area, physical, and electrical properties of MoC films was investigated. MoC thin films deposited by the unbalanced magnetron sputtering method exhibited a smooth and uniform surface. However, as the graphite target power density increased, the rms surface roughness of the MoC film increased, and the hardness and elastic modulus of the MoC thin film increased. Additionally, as the graphite target power density increased, the resistivity value of the MoC film increased. In the performance of an organic thin film transistor using a MoC gate electrode, the carrier mobility, threshold voltage, and drain current on/off ratio (I_on/I_off) showed 0.15 cm²/V·s, -5.6 V, and 7.5×10⁴, respectively.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.154-154
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• 2012

Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.126-126
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• 2018

최근 차세대 디스플레이인 flexible 하고 transparent 한 디스플레이 개발이 진행 중 이며, 이러한 디스플레이가 개발 되기 위해 백 플레인으로 사용되는 Thin Film Transistor (TFT) 또한 차세대 디스플레이 못지 않게 연구가 진행 되고 있다. 기존의 무기물을 기반으로 하고 Rigid한 TFT는 현재 많은 곳에 적용이 되어 사람들이 사용 하고 있다. 하지만 이미 시장은 포화상태이며 차세대 디스플레이 컨셉인 flexible 하고 투명한 것과 맞지 않는다. 그래서 유연하며 투명한 특성을 가진 TFT에 대한 연구가 활발히 진행 되고 있으며 많은 성과를 이루었다. 이러한 소자를 이용하여 훗날 Electronic-skin(e-skin)이라 부르는 전자 피부를 활용하여 실시간 모니터링 할 수 있는 헬스 케어 분야 등에 활용 가치 또한 높다. 현재 유연하며 투명한 기판 및 물질 개발에 많은 연구 개발이 진행 되고 있다. 하지만 유연한 기판을 사용하여 TFT를 제작한 후 stress나 bending에 대한 내구성과 안정성, 신뢰성 등이 무기물을 기반으로 한 TFT에 비해 좋지 않은 실정이다. 따라서 유연하며 투명한 기판을 사용한 TFT에 대한 안정성, 신뢰성 등을 확보하여야 한다. 본 연구 에서는 유연한 기판을 사용하여 TFT를 제작 한 후, TFT특성과 안정성을 확보하는 것을 목표로 실험을 진행하였다. 우리는 Mo전극과 Parylene 기판을 사용하여 유연한 TFT소자를 탑 게이트 구조로 제작 하였고 Rigid한 Glass기판 위에 Floating Process를 진행하기 위해 PVA층을 코팅 후 그 위에 Parylene을 CVD로 증착 하고 IGZO를 Sputter를 사용해 증착했다. Parylene은 DI Water 70도에서 Floating 공정을 통해 Rigid 기판에서 탈착 시켰다. 유연한 기판 위에 TFT를 제작 후 bending에 대한 특성 변화 및 안정성에 대한 측정을 실시하였다. Bending에 대한 특성 변화는 우수한 결과가 나왔지만 안정성 측정 중 Negative Bias Stress(NBS) 상에서 비정상적인 On Current Drop 현상이 발생 되었다. Parylene과 Channel층 사이 interface roughness로 인해 charge trap이 되고 이로 인해 On Current Drop 이라는 현상으로 나타났다. 그래서 우리는 Parylene 기판과 Channel 층간의 surface roughness를 개선하기 위한 방법으로 UV Treatment를 사용하였고 시간을 다르게 하여 surface 개선을 진행했다. Treatment 시간을 증가 시킴에 따라 Surface roughness가 많이 좋아 졌으며, Surface를 개선하고자 비정상적인 On Current Drop 현상이 없어졌으며 위 실험으로 Polymer의 surface roughness에 따라 TFT에 대한 안정성에 대한 신뢰성이 확보 될 수 있는 것을 확인 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03a
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• pp.17-17
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• 2010

The amorphous $Bi_5Nb_3O_{15}$ film grown at room temperature under an oxygen-plasma sputtering ambient (BNRT-$O_2$ film) has a hydrophobic surface with a surface energy of $35.6\;mJm^{-2}$, which is close to that of the orthorhombic pentacene ($38\;mJm^{-2}$, resulting in the formation of a good pentacene layer without the introduction of an additional polymer layer. This film was very flexible, maintaining a high capacitance of $145\;nFcm^{-2}$ during and after 10s bending cycles with a small curvature radius of 7.5 mm. This film was optically transparent. Furthermore, the flexible, pentacene-based, organic thin-film transistors (OTFTs) fabricated on the polyethersulphone substrate at room temperature using a BNRT-$O_2$ film as a gate insulator exhibited a promising device performance with a high field effect mobility of $0.5\;cm^2V^{-1}s^{-1}$, an on/off current modulation of $10^5$ and a small subthreshold slope of $0.2\;Vdecade^{-1}$ under a low operating voltage of -5 V. This device also maintained a high carrier mobility of $0.45\;cm^2V^{-1}s^{-1}$ during the bending with a small curvature radius of 9 mm. Therefore, the BNRT-$O_2$ film is considered a promising material for the gate insulator of the flexible, pentacene-based OTFT.

• Journal of Information Display
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• v.10 no.3
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• pp.131-136
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• 2009

This is a report on the fabrication of a flexible OTFT backplane for electrophoretic display (EPD) using a printing technology. A practical printing technology for a polycarbonate substrate was developed by combining the conventional screen and inkjet printing technologies with the wet etching and oxygen plasma processes. For the gate electrode, the screen printing technology with Ag ink was developed to define the minimum line width of ${\sim}5{\mu}m$ and the thickness of ${\sim}70nm$ with the resistivity of ${\sim}10^{-6}{\Omega}{\cdot}cm$, which are suitable for displays with SVGA resolution. For the source and drain (S/D) electrodes, PEDOT:PSS, whose conductivity was drastically enhanced to 450 S/cm by adding 10 wt% glycerol, was adopted. In addition, the modified PEDOT:PSS could be neatly confined in the specific S/D electrode area that had been pretreated with oxygen. The OTFTs that made use of the developed printing technology produced a mobility of ${\sim}0.13cm^2/Vs.ec$ and an on/off current ratio of ${\sim}10^6$, which are comparable to those using thermally evaporated Au for the S/D electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.202-205
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• 2002

Polycrystalline silicon thin film transistors (poly-Si TFTs) are used in a wide variety of applications, and will figure prominently future high-resolution, high-performance flat panel display technology However, it was very difficult to fabricate high performance poly-Si TFTs at a temperature lower than 300$^{\circ}C$ for glass substrate. Conventional process on a glass substrate were limited temperature less than 600$^{\circ}C$ This paper proposes a high temperature process above 750$^{\circ}C$ using a flexible molybdenum substrate deposited hydrogenated amorphous silicon (a-Si:H) and than crystallized a rapid thermal processor (RTP) at the various temperatures from 750$^{\circ}C$ to 1050$^{\circ}C$. The high temperature annealed poly-Si film illustrated field effect mobility higher than 30 $\textrm{cm}^2$/Vs, achieved I$\sub$on//I$\sub$off/ current ratio of 10$^4$ and crystall volume fraction of 92%. In this paper, we introduce the new TFTs Process as flexible substrate very promising roll-to-roll process, and exhibit the properties of high temperature crystallized poly-Si Tn on molybdenum substrate.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.19.1-19.1
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• 2010

The process of manufacturing printed electronics using printing technology is attracting attention because its process cost is lower than that of the conventional semiconductor process. This technology, which offers both a lower cost and higher productivity, can be applied in the production of organic TFT (thin film transistor), solar cell, RFID(radio frequency identification) tag, printed battery, E-paper, touch screen panel, black matrix for LCD(liquid crystal display), flexible display, and so forth. In general, in order to implement printed electronics, narrow width and gap printing, registration of multi-layer printing by several printing units, and printing accuracy of under $20\;{\mu}m$ are all required. These electronic products require high precision to the degree of tens of microns - in a large area with flexible material, and mass productivity at low cost. As such, the roll-to-roll printing process is attracting attention as a mass production system for these printed electronic devices. For the commercialization of this process, two basic electronic ink technologies, such as conductive ink and polymers, and printing equipment have to be developed. Therefore, this paper addressed basis design and test to develop fine patterning equipment employing the roll-to-roll printing equipment and electronic ink.