• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.5C
• /
• pp.386-394
• /
• 2008

For digital holographic video system, it is important to generate digital hologram as fast as possible. This paper proposed a fixed-point method and fast generation method that can calculate the Fresnel hologram using operation of whole-coordinate recursive addition. To compute the digital hologram, 3D object is assumed to be a collection of depth-map point generated using a PC. Our algorithm can compute a phase on a hologram by recursive addition with fixed-point format at a high speed. When we operated this algorithm on a personal computer, we could maximally compute digital hologram about 70% faster than conventional method and about 30% faster than of [3]'s method.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.6
• /
• pp.1195-1201
• /
• 2005

This paper deals with procedures and results for teal time implementation of G.729 speech coder and channel coder including convolution codec, viterbi decoder, and interleaver using a fixed point DSP chip for radio communication systems. We described the method for real-time implementation based on integer simulation results and explained the implemented results by quality performance and required complexity for real-time operation. The required complexity was 24MIPS and 9MIPS in computational load, and 12K words and 4K words in execution code length for speech and channel. The functional evaluation was performed into two steps. The one was bit exact comparison with a fixed point C code, the other was executed by actual speech samples and error test vectors. Unlik other results such as individual implementation, We implemented speech and channel coders on a DSP chip with 160MIPS computation capability and 64 K words memory on chip. This results outweigh the conventional methods in the point of system complexity and implementation cost for radio communication system.

• Proceedings of the KSR Conference
• /
• 1998.11a
• /
• pp.255-261
• /
• 1998

The train automatic operation control system is an on-board train control system that is widely adopted in modern rapid transit systems. The control system consists of TCMS(Train Control and Monitoring System), ATC(Automatic Train Control), ATO(Automatic Train Operation) and TWC(Train to wayside communication) in the train and wayside facilities. The functions of the system is to regulate train riding comfort, to service limited speed and smoothness during start, acceleration, constant speed travel, and fixed point parking under the corresponding commands. The paper describes the simulation model of the train automatic operation control of subway system, configuration of simulator hardware and software and operational algorithms.

• The KIPS Transactions:PartB
• /
• v.13B no.4 s.107
• /
• pp.429-438
• /
• 2006

Neural Networks(NNs) are applied for solving a wide variety of nonlinear problems in several areas, such as image processing, pattern recognition etc. Although NN can be simulated by using software, many potential NN applications required real-time processing. Thus they need to be implemented as hardware. The hardware implementation of multi-layer perceptrons(MLPs) in several kind of NNs usually uses a fixed-point arithmetic due to a simple logic operation and a shorter processing time compared to the floating-point arithmetic. However, the fixed-point arithmetic-based MLP has a drawback which is not able to apply the MLP software that use floating-point arithmetic. We propose a design method for MLPs which has the floating-point arithmetic-based fully-pipelining architecture. It has a processing speed that is proportional to the number of the hidden nodes. The number of input and output nodes of MLPs are generally constrained by given problems, but the number of hidden nodes can be optimized by user experiences. Thus our design method is using optimized number of hidden nodes in order to improve the processing speed, especially in field of a repeated processing such as image processing, pattern recognition, etc.

• Transactions of the Korean Society of Mechanical Engineers
• /
• v.11 no.6
• /
• pp.971-974
• /
• 1987

Considering heat transfer and heat loss processes for the heat engine operating between two fixed heat reservoirs, it may be qualitatively explained that the maxima of power output and its efficiency depending upon operating conditions are extreme maxima. Furthermore, it is also found that from an economic point of view the above two extremes are related to extreme minima of plant cost per unit power output and operation cost per unit power output respectively, and the condition of minimum cost per unit power output exists between the extreme minimum conditions of plant cost per unit power output and that of operation cost per unit power output.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.1
• /
• pp.1-8
• /
• 2018

Recently, the convolutional neural network shows high performance in many computer vision tasks. However, convolutional neural networks require enormous amount of operation, so it is difficult to adopt them in the embedded environments. To solve this problem, many studies are performed on the ASIC or FPGA implementation, where an efficient representation method is required. The fixed-point representation is adequate for the ASIC or FPGA implementation but causes a performance degradation. This paper proposes a separate optimization of representations for the convolutional layers and the batch normalization layers. With the proposed method, the required bit width for the convolutional layers is reduced from 16 bits to 10 bits for the ResNet-50 neural network. Since the computation amount of the convolutional layers occupies the most of the entire computation, the bit width reduction in the convolutional layers enables the efficient implementation of the convolutional neural networks.

• Journal of Digital Convergence
• /
• v.17 no.10
• /
• pp.251-258
• /
• 2019

In the future, various products are created in various fields using artificial intelligence. In this age, it is a very important problem to know the operation principle of artificial intelligence learning method and to use it correctly. This paper introduces artificial intelligence learning methods that have been known so far. Learning of artificial intelligence is based on the fixed point iteration method of mathematics. The GD(Gradient Descent) method, which adjusts the convergence speed based on the fixed point iteration method, the Momentum method to summate the amount of gradient, and finally, the Adam method that mixed these methods. This paper describes the advantages and disadvantages of each method. In particularly, the Adam method having adaptivity controls learning ability of machine learning. And we analyze how these methods affect digital signals. The changes in the learning process of digital signals are the basis of accurate application and accurate judgment in the future work and research using artificial intelligence.

• Journal of Institute of Control, Robotics and Systems
• /
• v.15 no.11
• /
• pp.1137-1143
• /
• 2009

This paper presents the FPGA implementation of efficient algorithms for approximating exponential function based on floating point format data. The Taylor-Maclaurin expansion as a conventional approximation method becomes inefficient since high order expansion is required for the large number to satisfy the approximation error. A format converter is designed to convert fixed data format to floating data format, and then the real number is separated into two fields, an integer field and an exponent field to separately perform mathematic operations. A new assembly command is designed and added to previously developed command set to refer the math table. To test the proposed algorithm, assembly program has been developed. The program is downloaded into the Altera DSP KIT W/STRATIX II EP2S180N Board. Performances of the proposed method are compared with those of the Taylor-Maclaurin expansion.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.9 no.6
• /
• pp.335-344
• /
• 2014

As a kind of 2D spatial coordinate transform, image warping is a basic image processing technique utilized in various applications. Though image warping algorithm is composed of relatively simple operations such as memory accesses and computations of weighted average, real-time implementations on embedded vision systems suffer from limited computational power because the simple operations are iterated as many times as the number of pixels. This paper presents a real-time implementation of a look-up table(LUT)-based image warping using an FPGA. In order to ensure sufficient data transfer rate from memories storing mapping LUT and image data, appropriate memory devices are selected by analyzing memory access patterns in an LUT-based image warping using backward mapping. In addition, hardware structure of a parallel and pipelined architecture is proposed for fast computation of bilinear interpolation using fixed-point operations. Accuracy of the implemented hardware is verified using a synthesized test image, and an application to real-time lens distortion correction is exemplified.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.105-113
• /
• 2004

This paper proposes 3D graphics accelerator, especially rendering unit, for portable devices. The existing 3D architecture is not suitable for portable devices because of its huge size. To reduce the size, we use iterative architecture and fixed-point calculation. In this paper, we suggest the format of fixed-point comparing with the result images, and some special technique to control. Finally, it is implemented with FPGA and 0.25um ASIC technology respectively. The ASIC chip can execute 47.88M pixels per second. The size of ASIC chip is 4.9287mm*4.9847mm and the power consumption is 263.7mW with 50MHz operation frequency.