• Title/Summary/Keyword: Finite State Machine(FSM)

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The Design and Implementation of ECU Simulator for the Smart Vehicle based on FOTA (FOTA 기반 지능형 자동차를 위한 범용 ECU 시뮬레이터 설계 및 구현)

  • Park, In-Hye;Ko, Jae-Jin;Kwak, Jae-Min
    • Journal of Advanced Navigation Technology
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    • v.18 no.1
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    • pp.22-28
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    • 2014
  • This paper presents the design and development of ECU simulator in order to verify automatic firmware update system of ECU SW on the vehicle. We designed and developed general-proposed ECU simulator as devide into HW and SW parts. HWadopt 32bit MPU, CAN, LIN, LCD, and touch-pad button to satisfy general-proposed ECU level. And SW constructed as finite-state-machine structure in order to support HW spec. We developed ECU manager which deliveries update data to verify validity of operation. And we tested ECU simulator with ECU manager. For test of validity of ECU simulator, we set 4 scenarios between ECU simulator and manager. As the result, we confirmed validity of operation in ECU simulator for automatic SW update system.

Comparative analysis of the digital circuit designing ability of ChatGPT (ChatGPT을 활용한 디지털회로 설계 능력에 대한 비교 분석)

  • Kihun Nam
    • The Journal of the Convergence on Culture Technology
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    • v.9 no.6
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    • pp.967-971
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    • 2023
  • Recently, a variety of AI-based platform services are available, and one of them is ChatGPT that processes a large quantity of data in the natural language and generates an answer after self-learning. ChatGPT can perform various tasks including software programming in the IT sector. Particularly, it may help generate a simple program and correct errors using C Language, which is a major programming language. Accordingly, it is expected that ChatGPT is capable of effectively using Verilog HDL, which is a hardware language created in C Language. Verilog HDL synthesis, however, is to generate imperative sentences in a logical circuit form and thus it needs to be verified whether the products are executed properly. In this paper, we aim to select small-scale logical circuits for ease of experimentation and to verify the results of circuits generated by ChatGPT and human-designed circuits. As to experimental environments, Xilinx ISE 14.7 was used for module modeling, and the xc3s1000 FPGA chip was used for module embodiment. Comparative analysis was performed on the use area and processing time of FPGA to compare the performance of ChatGPT products and Verilog HDL products.