• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.3
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• pp.387-393
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• 2015

In Electronic Commerce and Secret Communication based on ECC over finite field, if the sender and the receiver use different basis of finite fields, then the time of communication should always be delayed. In this paper, we analyze the number of bases-transformations needed for Electronic Signature in Electronic Commerce and Secret Communication based on ECC over finite field between H/W and S/W implementation systems and introduce the anomalous basis of finite fields using AOP which is efficient for H/W, S/W implementation systems without bases-transformations for Electronic Commerce and Secret Communication. And then we propose a new multiplier based on the anomalous basis of finite fields using AOP which reduces the running time by 25% than that of the multiplier based on finite fields using trinomial with polynomial bases.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.529-532
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• 2004

The ECC(Elliptic Curve Cryptogrphics), one of the representative Public Key encryption algorithms, is used in Digital Signature, Encryption, Decryption and Key exchange etc. The key operation of an Elliptic curve cryptosystem is a scalar multiplication, hence the design of a scalar multiplier is the core of this paper. Although an Integer operation is computed in infinite field, the scalar multiplication is computed in finite field through adding points on Elliptic curve. In this paper, we implemented scalar multiplier in Elliptic curve based on the finite field GF($2^{163}$). And we verified it on the Embedded digital system using Xilinx FPGA connected to an EISC MCU. If my design is made as a chip, the performance of scalar multiplier applied to Samsung $0.35 {\mu}m$ Phantom Cell Library is expected to process at the rate of 8kbps and satisfy to make up an encryption processor for the Embedded digital doorphone.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.747-755
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• 1990

In this paper, we presented a method of constructing a multiplier and an inverse element generator over finite field GF(3**m). We proposed the multiplication method using a descending order arithmetics of mod F(X) to perform the multiplication and mod F(X) arithmetics at the same time. The proposed multiplier is composed of following parts. 1) multiplication part, 2) data assortment generation part and 5) multiplication processing part. Also the inverse element generator is constructed with following parts. 1) multiplier, 2) group of output registers Rs, 3) multiplication and cube selection gate Gl, 4) Ri term sequential selection part. 5) cube processing part and 6) descending order mod F(X) generation part. Especially, the proposed multiplier and inverse element generator give regularity, expansibility and modularity of circuit design.

• Journal of the Korea Society of Computer and Information
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• v.25 no.1
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• pp.13-19
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• 2020

In this paper, we propose a multiplexer based scheme that performs modular AB² multiplication using redundant basis over finite field. Then we propose an efficient multiplexer based semi-systolic AB² multiplier using proposed scheme. We derive a method that allows the multiplexers to perform the operations in the cell of the modular AB² multiplier. The cell of the multiplier is implemented using multiplexers to reduce cell latency. As compared to the existing related structures, the proposed AB² multiplier saves about 80.9%, 61.8%, 61.8%, and 9.5% AT complexity of the multipliers of Liu et al., Lee et al., Ting et al., and Kim-Kim, respectively. Therefore, the proposed multiplier is well suited for VLSI implementation and can be easily applied to various applications.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.10a
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• pp.229-233
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• 1990

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.726-736
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• 2004

In this paper, we proposed a new scalar multiplier structure needed for an elliptic curve cryptosystem(ECC) over the standard basis in GF(2$^{163}$ ). It consists of a bit-serial multiplier and a divider with control logics, and the divider consumes most of the processing time. To speed up the division processing, we developed a new division algorithm based on the extended Euclid algorithm. Dynamic data dependency of the Euclid algorithm has been transformed to static and fixed data flow by a localization technique, to make it independent of the input and field polynomial. Compared to other existing scalar multipliers, the new scalar multiplier requires smaller gate counts with improved processor performance. It has been synthesized using Samsung 0.18 um CMOS technology, and the maximum operating frequency is estimated 250 MHz. The resulting performance is 148 kbps, that is, it takes 1.1 msec to process a 163-bit data frame. We assure that this performance is enough to be used for digital signature, encryption/decryption, and key exchanges in real time environments.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.2
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• pp.37-44
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• 2001

In this paper, an efficient architecture for the ECC multiplier in GF(2") is proposed. We give a design example for the irreducible trinomials $x_{193}\;+\;x_{15}\;+\;1$. In hardware implementations, it is often desirable to use the irreducible trinomial equations. A digit-serial multiplier with a digit size of 32 is proposed, which has more advantages than the 193bit serial LFSR architecture. The proposed multiplier is verified with a VHDL description using an elliptic curve addition. The elliptic curve used in this implementation is defined by Weierstrass equations. The measured results show that the proposed multiplier it 0.3 times smaller than the bit-serial LFSR multiplier.lier.

• Journal of Ocean Engineering and Technology
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• v.10 no.3
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• pp.96-104
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• 1996

Hamilton's principle is used to derive Euler-Lagrange equations for free surface flow problems of incompressible ideal fluid. The velocity field is chosen to satisfy the continuity equation a priori. This approach results in a hierarchial set of governing equations consist of two evolution equations with respect to two canonical variables and corresponding boundary value problems. The free surface elevation and the Lagrange's multiplier are the canonical variables in Hamilton's sense. This Lagrange's multiplier is a velocity potential defined on the free surface. Energy is conserved as a consequence of the Hamiltonian structure. These equations can be applied to waves in water of finite depth including generalization of Hamilton's equations given by Miles and Salmon.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.51-58
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• 2004

Most of pubic-key cryptosystems are built on the basis of arithmetic operations defined over the finite field GF$GF(2^m)$ .The other operations of finite fields except addition can be computed by repeated multiplications. Therefore, it is very important to implement the multiplication operation efficiently in public-key cryptosystems. We propose an efficient bit-parallel normal basis multiplier for$GF(2^m)$ fields defined by All-One Polynomials. The gate count and time complexities of our proposed multiplier are lower than or equal to those of the previously proposed multipliers of the same class. Also, since the architecture of our multiplier is regular, it is suitable for VLSI implementation.