• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.51-55
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• 2007

This paper investigates the subthreshold behavior of Fin Field Effect Transistor (FinFET). The FinFET is considered to be an alternate MOSFET structure for the deep sub-micron regime, having excellent device characteristics. As the channel length decreases, the study of subthreshold behavior of the device becomes critically important for successful design and implementation of digital circuits. An accurate analysis of subthreshold behavior of FinFET was done by simulating the device in a 3D process and device simulator, Taurus. The subthreshold behavior of FinFET, was measured using a parameter called S-factor which was obtained from the $In(I_{DS})\;-\;V_{GS}$ characteristics. The value of S-factor of devices of various fin dimensions with channel length $L_g$ in the range of 20 nm - 50 nm and with the fin width $T_{fin}$ in the range of 10 nm - 40 nm was calculated. It was observed that for devices with longer channel lengths, the value of S-factor was close to the ideal value of 60 m V/dec. The S-factor increases exponentially for channel lengths, $L_g\;<\;1.5\;T_{fin}$. Further, for a constant $L_g$, the S factor was observed to increase with $T_{fin}$. An empirical relationship between S, $L_g$ and $T_{fin}$ was developed based on the simulation results, which could be used as a rule of thumb for determining the S-factor of devices.

• Electronics and Telecommunications Trends
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• v.38 no.6
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• pp.52-61
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• 2023

With semiconductor scaling approaching the physical limits, devices including CMOS (complementary metal-oxide-semiconductor) components have managed to overcome yet are currently struggling with several technical issues like short-channel effects. Evolving from the process node of 22 nm with FinFET (fin field effect transistor), state-of-the-art semiconductor technology has reached the 3 nm node with the GAA-FET (gate-all-around FET), which appropriately addresses the main issues of power, performance, and cost. Technical problems remain regarding the foundry of GAA-FET, and next-generation devices called post-GAA transistors have not yet been devised, except for the CFET (complementary FET). We introduce a CFET that spatially stacks p- and n-channel FETs on the same footprint and describe its structure and fabrication. Technical details like stacking of nanosheets, special spacers, hetero-epitaxy, and selective recess are more thoroughly reviewed than in similar articles on CFET fabrication.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Journal of Convergence for Information Technology
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• v.11 no.11
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• pp.159-165
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• 2021

A fin channel with a fin width of 20 nm and a gradually increased source/drain extension regions are fabricated on a bulk silicon wafer by using a three-dimensional selective oxidation. The detailed process steps to fabricate the proposed fin channel are explained. We are demonstrating their preliminary characteristics and properties compared with those of the conventional fin field effect transistor device (FinFET) and the bulk FinFET device via three-dimensional device simulation. Compared to control devices, the three-dimensional selective oxidation fin channel MOSFET shows a higher linear transconductance, larger drive current, and lower series resistance with nearly the same scaling-down characteristics.

• Journal of Applied Reliability
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• v.10 no.1
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Vacuum Magazine
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• v.3 no.1
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• pp.16-21
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• 2016

FinFETs are able to be scaled down to 22 nm and beyond while suppressing effectively short channel effect, and have superior performance compared to 2-dimensional (2-D) MOSFETs. Bulk FinFETs are built on bulk Si wafers which have less defect density and lower cost than SOI(Silicon-On-Insulator) wafers. In contrast to SOI FinFETs, bulk FinFETs have no floating body effect and better heat transfer rate to the substrate while keeping nearly the same scalability. The bulk FinFET has been developed at 14 nm technology node, and applied in mass production of AP and CPU since 2015. In the development of the bulk FinFETs at 10 nm and beyond, self-heating effects (SHE) is becoming important. Accurate control of device geometry and threshold voltage between devices is also important. The random telegraph noise (RTN) would be problematic in scaled FinFET which has narrow fin width and small fin height.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.191-197
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• 2016

In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.34 no.5
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• pp.296-300
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• 2021

The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.508-517
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• 2014

We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width ($W_{fin}$) and height ($H_{fin}$) of the fin as well as the channel doping concentration ($N_{ch}$). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.