• Journal of Korea Society of Digital Industry and Information Management
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• v.18 no.1
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• pp.1-9
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• 2022

Galois field arithmetic is important in error correcting codes and public-key cryptography schemes. Hardware realization of these schemes requires an efficient implementation of Galois field arithmetic operations. Multiplication is the main finite field operation and designing efficient multiplier can clearly affect the performance of compute-intensive applications. Diverse algorithms and hardware architectures are presented in the literature for hardware realization of Galois field multiplication to acquire a reduction in time and area. This paper presents a low complexity semi-systolic multiplier to facilitate parallel processing by partitioning Montgomery modular multiplication (MMM) into two independent and identical units and two-level systolic computation scheme. Analytical results indicate that the proposed multiplier achieves lower area-time (AT) complexity compared to related multipliers. Moreover, the proposed method has regularity, concurrency, and modularity, and thus is well suited for VLSI implementation. It can be applied as a core circuit for multiplication and division/exponentiation.

• ETRI Journal
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• v.35 no.3
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• pp.523-529
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• 2013

Subquadratic space complexity multipliers for optimal normal bases (ONBs) have been proposed for practical applications. However, for the Gaussian normal basis (GNB) of type t > 2 as well as the normal basis (NB), there is no known subquadratic space complexity multiplier. In this paper, we propose the first subquadratic space complexity multipliers for the type 4 GNB. The idea is based on the fact that the finite field GF($2^n$) with the type 4 GNB can be embedded into fields with an ONB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4C
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• pp.217-225
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• 2011

In this paper, we propose an adaptive de-interlacing algorithm that is based on the degree of local complexity. The conventional intra field de-interlacing algorithms show the different performance according to the ways which find the edge direction. Furthermore, FDD (Fine Directional De-interlacing) algorithm has the better performance than other algorithms but the computational complexity of FDD algorithm is too high. In order to alleviate these problems, the proposed algorithm selects the most efficient de-interacing algorithm among LA (Line Average), MELA (Modified Edge-based Line Average), and LCID (Low-Complexity Interpolation Method for De-interlacing) algorithms which have low complexity and good performance. The proposed algorithm is trained by the DoLC (Degree of Local Complexity) for selection of the algorithms mentioned above. Simulation results show that the proposed algorithm not only has the low complexity but also performs better objective and subjective image quality performances compared with the conventional intra-field methods.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.4
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• pp.227-233
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• 2016

Efficient finite field arithmetic is essential for fast implementation of error correcting codes and cryptographic applications. Among the arithmetic operations over finite fields, the multiplication is one of the basic arithmetic operations. Therefore an efficient design of a finite field multiplier is required. In this paper, two new bit-parallel systolic multipliers for $GF(2^m)$ fields defined by AOP(all-one polynomial) have proposed. The proposed multipliers have a little bit greater space complexity but save at least 22% area complexity and 13% area-time (AT) complexity as compared to the existing multipliers using AOP. As compared to related works, we have shown that our multipliers have lower area-time complexity, cell delay, and latency. So, we expect that our multipliers are well suited to VLSI implementation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.16 no.2
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• The Journal of the Korea Contents Association
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• v.18 no.11
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• pp.484-492
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• 2018

This study examined the effects of field complexity and type of target objects on the performance in baggage screening task. A total of 62 participants(male: 45.2%, female: 54.8%) participated and their mean age was 22.88. The simulated baggage screening task was developed for this study and after the orientation and task exercises, main experiment session was conducted. Participants performed a total of 200 tasks and 40(20%) contained target object. The complexity was set at three levels: high, middle, and low levels and the number of background items contained 20, 14. and 8 respectively. The type of target was set as gun, knife, liquid, and righter. The dependent variables were hit ratio and reaction time. The results showed that the hit ratio decreased and reaction time increased significantly as field complexity increased, and they varied depending on the type of target. The hit ratio of the knife was the highest and liquid lowest and reaction time of the knife was the fastest and liquid slowest. In addition, the interaction effect was also significant. Knife was not affected by complexity, however, small item such as lighter was most affected by complexity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.118-125
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• 2016

This paper presents a new high-efficient algorithm and architecture for an elliptic curve cryptographic processor. To reduce the computational complexity, novel modified Lopez-Dahab scalar point multiplication and left-to-right algorithms are proposed for point multiplication operation. Moreover, bit-serial Galois-field multiplication is used in order to decrease hardware complexity. The field multiplication operations are performed in parallel to improve system latency. As a result, our approach can reduce hardware costs, while the total time required for point multiplication is kept to a reasonable amount. The results on a Xilinx Virtex-5, Virtex-7 FPGAs and VLSI implementation show that the proposed architecture has less hardware complexity, number of clock cycles and higher efficiency than the previous works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3B
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• pp.510-518
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• 2000

A new video interpolation technique based on variable skip rate of video sequence is proposed in this paper. in the proposed technique. the determination whether a frame is skipped or not is done by the degree of motion complexity of the frame. If the motion complexity of a frame is low the frame is skipped. otherwise it is coded and transmitted. To determine the motion complexity of a frame a new technique using MEF (moving edge in frame),the set of pixels considered as moving edges in a frame. is introduced. In the course of decoding and interpolating of receiver., the motion field is segmented. For the purpose of dividing vector field morphological filtering is applied. Morphological filtering also used to smooth the boundaries between the changed and unchanged region. In the simulation results, the proposed technique shows higher quality and lower fluctuation of picture quality than the conventional techniques on conditioning of the same bit rate.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2351-2369
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• 2012

This paper describes interpolation method of motion field in the Wyner-Ziv video coding (WZVC) based on Expectation-Maximization (EM) algorithm. In the EM algorithm, the estimated motion field distribution is calculated on a block-by-block basis. Each pixel in the block shares similar probability distribution, producing an undesired blocking artefact on the pixel-based motion field. The proposed interpolation techniques are Bicubic and Lanczos which successively use 16 and 32 neighborhood probability distributions of block-based motion field for one pixel in k-by-k block on pixel-based motion field. EM-based WZVC codec updates the estimated probability distribution on block-based motion field, and interpolates it to pixel resolution. This is required to generate higher-quality soft side information (SI) such that the decoding algorithm is able to make syndrome estimation more quickly. Our experiments showed that the proposed interpolation methods have the capability to reduce EM-based WZVC decoding complexity with small increment of bit rate.

• ETRI Journal
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• v.39 no.4
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• pp.570-581
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• 2017

Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations. Several systolic multipliers are proposed in the literature that offer low hardware complexity or high speed. In this paper, a bit-parallel polynomial basis systolic multiplier for generic irreducible polynomials is proposed based on a modified interleaved multiplication method. The hardware complexity and delay of the proposed multiplier are estimated, and a comparison with the corresponding multipliers available in the literature is presented. Of the corresponding multipliers, the proposed multiplier achieves a reduction in the hardware complexity of up to 20% when compared to the best multiplier for m = 163. The synthesis results of application-specific integrated circuit and field-programmable gate array implementations of the proposed multiplier are also presented. From the synthesis results, it is inferred that the proposed multiplier achieves low power consumption and low area complexitywhen compared to the best of the corresponding multipliers.