• Journal of the Korean Society for Heat Treatment
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• v.15 no.3
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• pp.113-117
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• 2002

Fatigue characteristics of ferroelectric $Pb(Zr,Ti)O_3$ (PZT) based capacitors through donor doping is reported in this paper. La substitution up to 10% were carried out to study systematically the fatigue behaviors of epitaxial ferroelectric capacitors grown on Si using $(Ti_{0.9}Al_{0.1})N/Pt$ conducting barrier composite. Ferroelectric capacitors substituted with 10% La show sufficient low voltage switched polarization and fatigue free performance. Systematic decrease in the tetragonality of the ferroelectric phase (i.e., c/a ratio) results in the corresponding reduction in coercive voltage, sufficient remnant polarization at 1.5-3V, and good fatigue property.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.101-102
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• 2006

PZT thin films, which are the representative ferroelectric materials in ferroelectric random access memory (FRAM), have some serious problem such as the imprint, retention and fatigue which ferroelectric properties are degraded by repetitive polarization. BL T thin film capacitors were fabricated by plasma etching, however, the plasma etching of BLT thin film was known to be very difficult. In our previous study, the ferroelectric materials such as PZT and BLT were patterned by chemical mechanical polishing (CMP) using damascene process to top electrode/ferroelectric material/bottom electrode. It is also possible to pattern the BLT thin film capacitors by CMP, however, the CMP damage was not considered in the experiments. The properties of BLT thin films were changed by the change of polishing pressure although the removal rate was directly proportional to the polishing pressure in CMP process.

• The Korean Journal of Ceramics
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• v.6 no.2
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• pp.138-142
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• 2000

Thin film $LiNbO_3$MFS (metal-ferroelectric-semiconductor) capacitor showed improved characteristics such as low interface trap density, low interaction with Si substrate, and large remanent polarization. This paper reports ferroelectric $LiNbO_3$thin films grown directly on p-type Si (100) substrates by 13.56 MHz RF magnetron sputtering system for FRAM (ferroelectric random access memory) applications. RTA (rapid thermal anneal) treatment was performed for as-deposited films in an oxygen atmosphere at $600^{\circ}C$ for 60sec. We learned from X-ray diffraction that the RTA treated films were changed from amorphous to poly-crystalline $LiNbO_3$which exhibited (012), (015), (022), and (023) plane. Low temperature film growth and post RTA treatments improved the leakage current of $LiNbO_3$films while keeping other properties almost as same as high substrate temperature grown samples. The leakage current density of $LiNbO_3$films decreased from $10^{-5}$ to $10^{-7}$A/$\textrm{cm}^2$ after RTA treatment. Breakdown electric field of the films exhibited higher than 500 kV/cm. C-V curves showed the clockwise hysteresis which represents ferroelectric switching characteristics. Calculated dielectric constant of thin film $LiNbO_3$illustrated as high as 27.9. From ferroelectric measurement, the remanent polarization and coercive field were achieved as 1.37 $\muC/\textrm{cm}^2$ and 170 kV/cm, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.3
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• pp.2131-2134
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• 2015

In this study, It has been demonstrated a new and realizable possibility of the ferroelectric random access memory devices by all solution processing method with paper substrates. Organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) thin films were formed on paper substrate with Al electrode for the bottom gate structure using spin-coating technique. Then, they were subjected to annealing process for crystallization. The fabricated PVDF-TrFE thin films were observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM). It was found from polarization versus electric field (P-E) measurement that a PVDF-TrFE thin film on paper substrate showed very good ferroelectric property. This result agree well with that of a PVDF-TrFE thin film fabricated on the rigid Si substrate. It anticipated that these results will lead to the emergence of printable electron devices on paper. Furthermore, it could be fabricated by a solution processing method for ferroelectric random access memory device, which is reliable and very inexpensive, has a high density, and can be also fabricated easily.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.2
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Proceedings of the Korean Magnestics Society Conference
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• 2002.12a
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• pp.188-189
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• 2002

One of the current goals in memory device developments is to realize a nonvolatile memory, i.e., the stored information maintains even when the power is turned off. The representative candidates for nonvolatile memories are magnetic random access memory (MRAM) and ferroelectric random access memory (FRAM). In order to achieve a high density memory in MRAM device, the external magnetic field should be localized in a tiny cell to control the direction of spontaneous magnetization. (omitted)

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.222-227
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• 2004

The sub-bitline (SBL) sensing voltage of a cell and total cell array can be measured by the method of SBL voltage evaluation method. The MOSAID tester can collect all SBL signals. The hierarchical bitline of unit cell array block is composed of the cell array of 2k rows and 128 columns, which is divided into 32 cell array sections. The unit cell array section is composed of the cell array of 64 rows and 128 columns. The average sensing voltage with 2Pr value of $5{\mu}C/cm^2$ and SBL capacitance of 40fF is about 700mV at 3.0V operation voltage. That is high compensation method for capacitor size degradation effect. Thus allowed minimum 2Pr value for high density Ferroelectric RAM (FeRAM) can move down to about less than $5{\mu}C/cm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.765-770
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• 2001

Metal-ferroelectric-insulator- semiconductor(MFTS) devices by using rapid thermal annealed (RTA) LiNbO$_3$/AIN/Si(100) structures were successfully fabricated and demonstrated nonvolatile memory operations. Metal-insulator-semiconductor(MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2 V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/$\textrm{cm}^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8 V, 50 % duty cycle) in the 500 kHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.570-576
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• 2007

In this study, the characteristics of metal-ferroelectric-semiconductor FET (MFSFET) device is investigated using field-dependent polarization and square-law FET models. From drain current with the gate voltage variation, when coercive voltages of ferroelectric thin film are 0.5 and 1V, the memory windows are 1 and 2V, respectively. When the gate voltages are 0, 0.1, 0.2 and 0.3V, the difference of saturation drain currents of the MFSFET device at two threshold voltages in ID-VD curve are 1.5, 2.7, 4.0, and 5.7mA, respectively. As a result of the analysis for drain currents after tine lapse, which is based on the simulation for hysteresis loop and the fitting of retention properties of ferroelectric thin films such as PLZT(10/30/70), PLT(10) and PZT(30/70) thin film shows excellent reliability that the decrease of saturation current is about 18% after 10 years.