• 한국HCI학회:학술대회논문집
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• 2007.02a
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• pp.790-795
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• 2007

최근 유비쿼터스 컴퓨팅에 대한 연구가 활발히 진행되고 있으며 유비쿼터스 컴퓨팅의 실현을 위한 핵심기술로서 RFID 시스템에 대한 연구가 활발히 진행되고 있다. 유비쿼터스 환경에서 RFID 시스템이 사용자의 편리함을 가져다 주는 장점이 있는 반면, 이로 인해 사용자의 프라이버시가 침해 당할 수 있는 문제점 또한 가지고 있다. 본 논문에서 사용자 인증 알고리즘은 새로운 해쉬 함수를 사용하고 그리고 메시지 암호화를 위한 스트림 암호기는 LFSR(Linear Feedback Shift Register)을 사용한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.7
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• pp.93-101
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• 2010

In this paper we generate Gold-sequence by using M-sequence which is made by two primitive polynomial of GF(2). Generally M-sequence is generated by linear feedback shift register code generator. Here we show that this matrix of appropriate permutation has Hadamard matrix property. This matrix proves that Gold-sequence through two M-sequence and additive matrix of one column has one of major properties of Hadamard matrix, orthogonal. and this matrix show another property that multiplication with one matrix and transpose matrix of this matrix have the result of unit matrix. Also M-sequence which is made by linear feedback shift register gets Hadamard matrix property mentioned above by adding matrices of one column and one row. And high-speed conversion is possible through L-matrix and the S-matrix.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.1-7
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• 1992

This paper proposes a built-in self-test tchnique for CMOS circuits. To detect a stuck-open fault in CMOS circuits, two consequent test patterns is required. The ordered pairs of test patterns for stuck-open faults are generated by feedback shift registers of extended length. A nonlinear feedback shift register is designed by the merging method and reordering algorithms of test patterns proposed in this paper. And a new multifunctional BILBO (Built-In Logic Block Observer) is designed to perform both test pattern generation and signature analysis efficiently.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.18-24
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• 2011

In multibit Sigma-Delta Modulator, one of the DEM(Dynamic Element Matching) techniques which is DWA(Data Weighted Averaging) is widely used to get rid of non-linearity caused by mismatching of capacitor that is unit element of feedback DAC. In this paper, by adjusting clock timing used in existing DWA architecture, 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. After designing the 3rd 3-bit SC(Switched Capacitor) Sigma-Delta Modulator by using the proposed DWA architecture, 0.1% of mismatching into unit element in input frequency 20 kHz and sampling frequency 2.56 MHz. As a consequence of the simulation, It was able to get the same resolution as the existing architecture and was able to reduce the number of MOS Tr. by 222.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.707-714
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• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7C
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• pp.663-670
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• 2009

In this paper, we propose the image encryption method which gradually uses NFSR(Non-linear Feedback Shift Register) and 20 CAT(Two-Dimensional Cellular Automata Transform). The encryption method is processed in the following order. First, NFSR is used to create a PN(pseudo noise) sequence, which matches the size of the original image. Then, the created sequence goes through a XOR operation with the original image and process the encipherment. Next, the gateway value is set to produce a 20 CAT basis function. The produced basis function is multiplied by encryption image that has been converted to process the 20 CAT encipherment. Lastly, the results of the experiment which are key space analysis, entropy analysis, and sensitivity analysis verify that the proposed method is efficient and very secure.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.6
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• pp.994-1001
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• 2001

In this paper, we propose the Improved SIR-based Power Control method in mobile communication system. Generally speaking, SIR-based design considering both channel noise and multiuser interference is accurate indication of signal quality and provides good performance. However, one serious problem associated with SIR-based Power Control is the potential of Positive Feedback which can endanger the stability of the system. Therefore from SIR definition, we decrease the signal\`s Interference we will got a improved SIR and have a stable power control Also in mobile using window register which has Up-Maintain-Down power control step size instead of Up-Down, we got a better performance. This paper assesses the performance of Improved SIR based Power Control using PIC and window register. The proposed Improved SIR based Power Control is presented and compared with existing SIR based Power Control and Strength-and-SIR based Power Control.

• Journal of Korea Society of Industrial Information Systems
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• v.10 no.3
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• pp.57-63
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• 2005

Kim and Fenn et al. proposed two modular AB multipliers based on LFSR(Linear Feedback Shift Register) architecture. These multipliers use AOP, which has all coefficients with '1', as an irreducible polynomial. Thereby, they have good hardware complexity compared to the previous architectures. This paper proposes a modular $AB^2$ multiplier based on LFSR architecture and a modular exponentiation architecture to improve the hardware complexity of the Kim's. Our multiplier also use the AOP as an irreducible polynomial as the Kim architecture. Simulation result shows that our multiplier reduces the hardware complexity about $50\%$ in the perspective of XOR and AND gates compared to the Kim's. The architecture could be used as a basic block to implement public-key cryptosystems.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.93-98
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• 2003

This paper presents two new algorithms and their architectures for $AB^2 $ multiplication over $GF(2^m)$.First, a new architecture with a new algorithm is designed based on LFSR (Linear Feedback Shift Register) architecture. Furthermore, modified $AB^2 $ multiplier is derived from the multiplier. The multipliers and the structure use AOP (All One Polynomial) as a modulus, which hat the properties of ail coefficients with 1. Simulation results thews that proposed architecture has lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponential ion architecture, which is the tore operation In public-key cryptosystems.