• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.2
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

• Journal of Digital Contents Society
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• v.13 no.1
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• pp.37-41
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• 2012

In this paper, we proposed FPGA algorithm for consider the power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within FPGA. Separated the feasible cluster reduced power consumption using glitch removal method. Glitch removal appled delay buffer insertion method by signal process within the feasible cluster. Also, removal glitch between the feasible clusters by signal process for circuit. The experiments results show reduction in the power consumption by 7.14% comparing with that of [9].

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.3
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• pp.69-75
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• 2009

In this paper, we proposed CPLD low power algorithm using reduce glitch power consumption. Proposed algorithm generated a feasible cluster by circuit partition considering the CLB condition within CPLD. Glitch removal process using delay buffer insertion method for feasible cluster. Also, glitch removal process using same method between feasible clusters. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off and a low power circuit design using selective glitch removal method. The experiments results show reduction in the power consumption by 15% comparing with that of and 6% comparing with that of.

• Transactions of the Korean Society of Automotive Engineers
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• v.12 no.6
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• pp.135-142
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• 2004

The severe frontal crash tests are NCAP with belted occupant at 35mph and FMVSS 208 with unbelted occupant at 25mph, This paper describes the design process of occupant protection systems, airbag and seat belt, under the two tests. In this study, NCAP simulations are performed by Monte Carlo search method and cluster analysis. The Monte Carlo search method is a global optimization technique and requires execution of a series of deterministic analyses, The procedure is as follows. 1) Define the region of interest 2) Perform Monte Carlo simulation with uniform distribution 3) Transform output to obtain points grouped around the local minima 4) Perform cluster analysis to obtain groups that are close to each other 5) Define the several feasible design ranges. The several feasible designs are acquired and checked under FMVSS 208 simulation with unbelted occupant at 25mph.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.131-135
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• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1165-1168
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.59-63
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• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.1-5
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• 2013

In this paper a study of efficient CPLD low power algorithm is proposed. Proposed algorithm applicate graph partition method using DAG. Circuit representation DAG. Each nodes set up cost. The feasible cluster create according to components of CPLD. Created feasible cluster generate power consumption consider the number of OR-term, the number of input and the number of output. Implement a circuit as select FC having the minimum power consumption. Compared with experiment [9], and power consumption was decreased. The proposed algorithm is efficient. this paper, we proposed FPGA algorithm for consider the power consumption.

• Journal of the Korean Institute of Intelligent Systems
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• v.5 no.2
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• pp.58-69
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• 1995

In this paper GFI (Generalized Fuzzy Isodata) and FI (Fuzzy Isodata) algorithms are studied and applied to the tire tread pattern classification problem. GFI algorithm which repeatedly grouping the partitioned cluster depending on the fuzzy partition matrix is general form of GI algorithm. In the constructing the binary tree using GFI algorithm cluster validity, namely, whether partitioned cluster is feasible or not is checked and construction of the binary tree is obtained by FDH clustering algorithm. These algorithms show the good performance in selecting the prototypes of each patterns and classifying patterns. Directions of edge in the preprocessed image of tire tread pattern are selected as features of pattern. These features are thought to have useful information which well represents the characteristics of patterns.

• Bulletin of the Korean Chemical Society
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• v.13 no.5
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• pp.482-486
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• 1992

Ion-molecule reactions of acetylene and mixed acetylene-ammonia cluster ions are studied using an electron impact time-of-flight mass spectrometer. The present results clearly demonstrate that $(C_2H_2)_n^+$ cluster ion distribution represents a distinct magic number of n=3. The mass spectroscopic evidence for the enhanced structural stabilities of $[C_6H_4{\cdot}(NH_3)_m]^+$ (m=0-8) ions is also found along with the detection of mixed cluster $[(C_2H_2)_n{\cdot}(NH_3)_m]^+$ ions, which gives insight into the feasible structure of solvated ions. This is rationalized on the basis of the structural stability for acetylene clusters and the dissociation dynamics of the complex ion under the presence of solvent molecules.