• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.7
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• pp.3747-3765
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• 2017

Existing authentication mechanisms in cellular mobile communication networks are realized in the upper layer by employing cryptographic techniques. Authentication data are broadcasted over the air in plaintext, enabling attackers to completely eavesdrop on the authentication and get some information about the shared secret key between legitimate nodes. Therefore, reusing the same secret key to authenticate several times results in the secret key's information leakage and high attacking rate. In this paper, we consider the most representative authentication mechanism, Authentication and Key Agreement (AKA), in cellular communication networks and propose an enhanced AKA scheme based on Physical Layer Authentication (AKA-PLA). Authentication responses generated by AKA are no longer transmitted in plaintext but masked by wireless channel characteristics, which are not available to adversaries, to generate physical layer authentication responses by a fault-tolerant hash method. The authenticator sets the threshold according to the authentication requirement and channel condition, further verifies the identity of the requester based on the matching result of the physical layer authentication responses. The performance analyses show that the proposed scheme can achieve lower false alarm rate and missing rate, which are a pair of contradictions, than traditional AKA. Besides, it is well compatible with AKA.

• Journal of Digital Convergence
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• v.17 no.1
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• pp.195-201
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• 2019

This paper proposes a blockchain system to share Wireless Local Area Network (WLAN) that recently suffers from mutual interference among increasing devices using unlicensed bands. Blockchain technology can induce cooperation from users by incentivizing them with cryptocurrency like shown in Bitcoin example. In this paper, we describe Blockchain based access mechanism in WLAN instead of conventional authentication based access. Here, users can access any WLAN access point by paying through smart contract while they also receive payment from others. In order to support real-time transaction, we apply proof-of-authority that is realized by Byzantine fault tolerant protocol instead of well-known proof-of-work that requires huge computing power and delay.

• International conference on construction engineering and project management
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• 2020.12a
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• pp.510-519
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• 2020

Within an intelligent automated cyber-physical system, the realization of the autonomous mechanism for data collection, data integration, and data analysis plays a critical role in the design, development, operation, and maintenance of such a system. This construct is particularly vital for fault-tolerant route-finding systems that rely on the imprecise GPS location of the vehicles to properly operate, timely plan, and continuously produce informative feedback to the user. More essentially, the integration of digital twins with cyber-physical route-finding systems has been overlooked in intelligent transportation services with the capacity to construct the network routes solely from the locations of the operating vehicles. To address this limitation, the present study proposes a conceptual architecture that employs digital twin to autonomously maintain, update, and manage intelligent transportation systems. This virtual management simulation can improve the accuracy of time-of-arrival prediction based on auto-generated routes on which the vehicle's real-time location is mapped. To that end, first, an intelligent transportation system was developed based on two primary mechanisms: 1) an automated route finding process in which predictive data-driven models (i.e., regularized least-squares regression) can elicit the geometry and direction of the routes of the transportation network from the cloud of geotagged data points of the operating vehicles and 2) an intelligent mapping process capable of accurately locating the vehicles on the map whereby their arrival times to any point on the route can be estimated. Afterward, the digital representations of the physical entities (i.e., vehicles and routes) were simulated based on the auto-generated routes and the vehicles' locations in near-real-time. Finally, the feasibility and usability of the presented conceptual framework were evaluated through the comparison between the primary characteristics of the physical entities with their digital representations. The proposed architecture can be used by the vehicle-tracking applications dependent on geotagged data for digital mapping and location tracking of vehicles under a systematic comparison and simulation cyber-physical system.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.520-533
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• 2007

The CRM(Customer Relationship Management) is the business strategy model for higher profits and competitive power of the enterprise in a new business environment. The large-scale customer response service technique uses internet, e-mail, SMS (Short Message Service), Telephony service, DM(Direct Mail) by customer channel point. Recently, business model diversify for new contract and retaining existing customer to the effort for a profitable model of business. This paper is based on Avaya PDS(Predictive Dialing System) model for CRM bond center. If the number of "available" agents are less than the number of inbound channels, then there may be real-time response problems in PDS system implemented. The Organization cannot afford to have many agents in available mode because of the high cost of manpower. This paper provides two contributions to the study. First, we present Call Object Management Mechanism of Customer Channel integration for reduce outbound consulting and reduce CallBack data in the PDS. Second, we design and implement the proposed system. Our simulation results show analysis of old model and proposed model. The proposed model can be efficiently used in Large-scale CRM.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.485-495
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• 2000

The parallel computer system that uses parallel program on the application such as a large scale business or complex operation is required. One of crucial operation of parallel computer system is synchronization. A representative method of synchronization is barrier synchronization. A barrier forces all process to wait until all the process reach the barrier and then releases all of the processes. There are software schemes, hardware scheme, or combinations of these mechanism to achieve barrier synchronization which tends to use hardware scheme. Besides, barrier synchronization lets parallel computer system fast because it has fewer start-up overhead. In this paper, we propose a new switch module that can implement fast and fault-tolerant barrier synchronization in hardware scheme. A proposed barrier synchronization is operated not in full-switch-driven method but in processor-driven method. An effective barrier synchronization is executed with inexpensive hardware supports. Therefore, a new proposed hardware barrier synchronization is designed that it is operated in arbitrary network topology. In this paper, we only show comparison of barrier synchronization on Multistage Interconnection Network. This research results in 24.6-24.8% reduced average delay. Through this result, we can expect lower average delay in irregular network.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.73-80
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• 2004

In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.