• Title/Summary/Keyword: Fault-Tolerant Cell Switching Network

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Reliability Analysis of the 2-Dimensional Ring-Banyan Network (2차원 링-밴얀 망의 신뢰성 분석)

  • Park, Jae-Hyun
    • Journal of KIISE:Information Networking
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    • v.34 no.4
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    • pp.256-261
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    • 2007
  • 2-Dimensional Ring-banyan network is a high-performance fault-tolerant switching network using a deflection self-routing. The throughput of the switching network is better than that of Cyclic Banyan network under non-uniform traffic. In this paper, we present an analytic reliability analysis of the fault-tolerant switching network. We present the Mean-Time-to-Failure that is calculated by using probabilistic model. This model also takes into account a hardware complexity. In case of $16\;{\times}\;16$ size, the presented switching network is 1.275 times more reliable than Hui's switching network. And it is 1.510 times more reliable than Hui's network in case of $64\;{\times}\;64$ size.

A High-Performance Fault-Tolerant Switching Network and Its Fault Diagnosis (고성능 결함감내 스위칭 망과 결함 진단법)

  • 박재현
    • Journal of KIISE:Information Networking
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    • v.31 no.3
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    • pp.335-346
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    • 2004
  • In this paper, we present a high-performance fault-tolerant switching networks using a deflection self-routing scheme, and present fault-diagnosis method for the network. We use the facts: 1) Each stage of the Banyan network is arrayed as the sequences of a Cyclic group of SEs. 2) There is the homomorphism between adjacent stages from a view of self-routing, so that all of each Cyclic group is the subgroup of the Cyclic group in the next stage, and there are factor groups due to such subgroup and homomorphism. We provide high-performance fault-tolerant switching networks of which the all links including augmented links are used as the alternate links detouring faulty links. We also present the fault diagnosis scheme for the proposed switching network that provide multiple paths for each input-output pair.

A Cost-Effective Dynamic Redundant Bitonic Sorting Network for ATM Switching (ATM 교환을 위한 비용 효율적인 동적 결함내성 bitonic sorting network)

  • Lee, Jae-Dong;Kim, Jae-Hong;Choe, Hong-In
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.4
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    • pp.1073-1081
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    • 2000
  • This paper proposes a new fault-tolerant technique for bitonic sorting networks which can be used for designing ATM switches based on Batcher-Banyan network. The main goal in this paper is to design a cost-effective fault-tolerant bitonic sorting network. In order to recover a fault, additional comparison elements and additional links are used. A Dynamic Redundant Bitonic Sorting (DRBS) network is based on the Dynamic Redundant network and can be constructed with several different variations. The proposed fault-tolerant sorting network offers high fault-tolerance; low time delays; maintenance of cell sequence; simple routing; and regularity and modularity.

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The Cell Resequencing Buffer for the Cell Sequence Integrity Guarantee for the Cyclic Banyan Network (사이클릭 벤얀 망의 셀 순서 무결성 보장을 위한 셀 재배열 버퍼)

  • 박재현
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.9
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    • pp.73-80
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    • 2004
  • In this paper, we present the cell resequencing buffer to solve the cell sequence integrity problem of the Cyclic banyan network that is a high-performance fault-tolerant cell switch. By offering multiple paths between input ports and output ports, using the deflection self-routing, the Cyclic banyan switch offer high reliability, and it also solves congestion problem for the internal links of the switch. By the way, these multiple paths can be different lengths for each other. Therefore, the cells departing from an identical source port and arriving at an identical destination port can reach to the output port as the order that is different from the order arriving at input port. The proposed cell resequencing buffer is a hardware sliding window mechanism. to solve such cell sequence integrity problem. To calculate the size of sliding window that cause the prime cost of the presented device, we analyzed the distribution of the cell delay through the simulation analyses under traffic load that have a nonuniform address distribution that express tile Property of traffic of the Internet. Through these analyses, we found out that we can make a cell resequencing buffer by which the cell sequence integrity is to be secured, by using a, few of ordinary memory and control logic. The cell resequencing buffer presented in this paper can be used for other multiple paths switching networks.