• Journal of KIISE:Computer Systems and Theory
• /
• 제26권9호
• /
• pp.1177-1184
• /
• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• Nuclear Engineering and Technology
• /
• 제51권3호
• /
• pp.692-701
• /
• 2019

Recently, instrumentation and control (I&C) systems in nuclear power plants have undergone digitalization. Owing to the unique characteristics of digital I&C systems, the reliability analysis of digital systems has become an important element of probabilistic safety assessment (PSA). In a reliability analysis of digital systems, fault-tolerant techniques and their effectiveness must be considered. A fault injection experiment was performed on a safety-critical digital I&C system developed for nuclear power plants to evaluate the effectiveness of fault-tolerant techniques implemented in the target system. A software-implemented fault injection in which faults were injected into the memory area was used based on the assumption that all faults in the target system will be reflected in the faults in the memory. To reduce the number of required fault injection experiments, the memory assigned to the target software was analyzed. In addition, to observe the effect of the fault detection coverage of fault-tolerant techniques, a PSA model was developed. The analysis of the experimental result also can be used to identify weak points of fault-tolerant techniques for capability improvement of fault-tolerant techniques

• Journal of Information Processing Systems
• /
• 제11권4호
• /
• pp.509-527
• /
• 2015

Wireless Video Sensor Networks (WVSNs) have become a leading solution in many important applications, such as disaster recovery. By using WVSNs in disaster scenarios, the main goal is achieving a successful immediate response including search, location, and rescue operations. The achievement of such an objective in the presence of obstacles and the risk of sensor damage being caused by disasters is a challenging task. In this paper, we propose a fault tolerance model of WVSN for efficient post-disaster management in order to assist rescue and preparedness operations. To get an overview of the monitored area, we used video sensors with a rotation capability that enables them to switch to the best direction for getting better multimedia coverage of the disaster area, while minimizing the effect of occlusions. By constructing different cover sets based on the field of view redundancy, we can provide a robust fault tolerance to the network. We demonstrate by simulating the benefits of our proposal in terms of reliability and high coverage.

• Journal of KIISE:Information Networking
• /
• 제36권4호
• /
• pp.339-350
• /
• 2009

In wireless sensor networks, the limited battery resources of sensor nodes have a direct impact on network lifetime. To reduce unnecessary power consumption, it is often the case that only a minimum number of sensor nodes operate in active mode while the others are kept in sleep mode. In such a case, however, the network service can be easily unreliable if any active node is unable to perform its sensing or communication function because of an unexpected failure. Thus, for achieving reliable sensing, it is important to maintain the sensing level even when some sensor nodes fail. In this paper, we propose a new fault-tolerance scheme, called FCP(Fault-tolerant Coverage Preserving), that gives an efficient way to handle the degradation of the sensing level caused by sensor node failures. In the proposed FCP scheme, a set of backup nodes are pre-designated for each active node to be used to replace the active node in case of its failure. Experimental results show that the FCP scheme provides enhanced performance with reduced overhead in terms of sensing coverage preserving, the number of backup nodes and the amount of control messages. On the average, the percentage of coverage preserving is improved by 87.2% while the additional number of backup nodes and the additional amount of control messages are reduced by 57.6% and 99.5%, respectively, compared with previous fault-tolerance schemes.

• Proceedings of the IEEK Conference
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.176-179
• /
• 2000

Fault simulation is often necessary to determine the fault coverage of a given test, that is, to find all the faults detected by test. In this paper we implement a deductive fault simulation using counting method. Counting method uses f$\sub$ｉ/ of fault table and Search list to compute set operation. f$\sub$ｉ/ was counted by fault list of input gate. And we propagate fault list from primary inputs toward primary output by comparing with controling sum. It improved performance by reducing search of faults.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• 제29A권8호
• /
• pp.99-109
• /
• 1992

First, the coupling faults of semiconductor memory are classified in detail. The chained coupling fault is introduced and defined, which results from sequential influencing of the coupling effects among memory cells, and its mapping relation is described. The linked coupling fault and its order are defined. Second, the deterministic “Algorithm GA” is proposed, which detects stuack-at faults, transition faults, address decoder faults, unlinked 2-coupling faults, and unlinked chained coupling faults. The time complexity and the fault coverage are improved in this algorithm. Third, it is proved that the march test of an address sequence can detect 97.796% of the linked 2-coupling faults with order 2. The deterministic “Algorithm NA” proposed can detect to the limit. The time complexity and the fault coverage are improved in this algorithm.

• Proceedings of the KSR Conference
• /
• 한국철도학회 1998년도 추계학술대회 논문집
• /
• pp.270-279
• /
• 1998

This paper presents the design of self-checking comparator using the time diversity and the application to 8 bit CPU for the implementation of fault tolerant computer system. this self-checking comparator was designed with the different time Points in which temporary faults were raised by electrical noise between duplicated functional blocks. also this self-checking comparator was simulated in the method of the fault injection using 4 bit shift register counter. we designed the duplicated Emotional block and the self-checking comparator in the single chip using the Altera EPLD and could verify the reliability and the fault detection coverage through the modeling of temporary faults ,especially intermittent faults. at the results of this research, the reliability and the fault detection coverage were implemented through the self-checking comparator using the time diversity.

• Journal of Institute of Control, Robotics and Systems
• /
• 제7권10호
• /
• pp.859-866
• /
• 2001

Recently, fault injection techniques are used for evaluation of the fault coverage properties of safety-critical systems. This paper describes the TCN Fault Injector(TFI) implemented for TCN safety analysis. The implemented TFI injects network level faults to Intelligent MVB Controller that is designed for the Korean High Speed Train. With TFI, it can be verified whether the MVB controller meets TCN specification and its safety requirements.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• 제34권11B호
• /
• pp.1133-1141
• /
• 2009

In this paper, we present a distributed fault-tolerant topology control protocol that configure a wireless sensor network to achieve k-connectivity and (k+1)-coverage. One fundamental issue in sensor networks is to maintain both sensing coverage and network connectivity in order to support different applications and environments, while some least active nodes are on duty. Topology control algorithms have been proposed to maintain network connectivity while improving energy efficiency and increasing network capacity. However, by reducing the number of links in the network, topology control algorithms actually decrease the degree of routing redundancy. Although the protocols for resolving such a problem while maintaining sensing coverage were proposed, they requires accurate location information to check the coverage, and most of active sensors in the constructed topology maintain 2k-connectivity when they keep k-coverage. We propose the fault-tolerant topology control protocol that is based on the theorem that k-connectivity implies (k+1)-coverage when the sensing range is at two times the transmission range. The proposed distributed algorithm does not need accurate location information, the complexity is O(1). We demonstrate the capability of the proposed protocol to provide guaranteed connectivity and coverage, through both geometric analysis and extensive simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• 제38권2호
• /
• pp.145-153
• /
• 2001

As combinational ATPG algorithms achieve effectively 100% fault coverage, reducing the length of test set without loosing its fault coverage becomes a challenging work. The new approach is based on the independent and the compatible relationships between faults. For more compact test set, the size of compatible fault set must be maximized, thus this algorithm generates fault-pattern pairs, and a fault-pattern pair tree structure using the independent and the compatible relationships between faults. With the fault-pattern pair tree structure, a compact test set effectively generated. The experimental results for ISCAS 85 and 89 benchmark circuits demonstrate the effectiveness of the proposed method.