• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.601-606
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• 2005

Recently with the high expectation of voice over WLAN service, to supped fast inter-AP security transition in WLAN AP is one of the most actively investigating issues. It is also very important to minimize inter-AP security transition latency, while maintaining constantly the secure association from old AP when a station transits to new AP. Hence, this paper first defines secure transition latency as a primary performance metric of AP system in WLAN supporting IEEE802.11i, 802.1x, and 802.11f, and then presents low latency inter-AP security transition mechanism and its security FSM whose objective is to minimize inter-AP transition latency. Experiment shows that the proposed scheme outperforms the legacy 802.1X AP up to $79\%$ with regard to the transition latency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.54-61
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for controller circuits is proposed. The proposed method always guarantees a short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The proposed method also shortens the test application time through a test pattern re-ordering procedure. The efficiency of the proposed method is demonstrated using well known MCNC'91 FSM benchmark circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Korean Journal of Computational Design and Engineering
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• v.13 no.3
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• pp.209-216
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• 2008

This paper presents a novel approach to design evaluation of portable consumer electronic (PCE) products using augmented reality (AR) based tangible interaction and functional behavior simulation. In the approach, the realistic visualization is acquired by overlaying the rendered image of a PCE product on the real world environment in real-time using computer vision based augmented reality. For tangible user interaction in an AR environment, the user creates input events by touching specified regions of the product-type tangible object with the pointer-type tangible object. For functional behavior simulation, we adopt state transition methodology to capture the functional behavior of the product into a markup language-based information model, and build a finite state machine (FSM) to controls the transition between states of the product based on the information model. The FSM is combined with AR-based tangible objects whose operation in the AR environment facilitates the realistic visualization and functional simulation of the product, and thus realizes faster product design and development. Based on the proposed approach, a product design evaluation system has been developed and applied for the design evaluation of various PCE products with highly encouraging feedbacks from users.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.7-12
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• 2011

Because development of high speed network, spread of internet, and high quality of computer performance, request and internet about massive multiplayer playing the game, is increasing. In order to experience realistic game play which is one of the most importance factor in massive multiplayer on-line, synchronization is importance matter. We propose synchronized and optimized scheme that combined FSM (Finite State Machine) and event holding method for efficient state synchronization for massive multiplayer on-line, and we show the effectiveness and reliability of our proposed scheme through the implementing and testing of the game server applying on our proposed scheme.

• Journal of Astronomy and Space Sciences
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• v.31 no.4
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• pp.341-346
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• 2014

A prototype of the GMT FSM has been developed to acquire and to enhance the key technology - mirror fabrication and tip-tilt actuation. The ellipsoidal off-axis mirror has been designed, analyzed, and fabricated from light-weighting to grinding, polishing, and figuring of the mirror surface. The mirror was tested by using an interferometer together with CGHs, which revealed the surface error of 13.7 nm rms in the diameter of 1030 mm. The SCOTS test was employed to independently validate the test results. It measured the surface error to be 17.4 nm rms in the diameter of 1010 mm. Both tests show the optical surface of the FSMP mirror within the required value of 20 nm rms surface error.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.2
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• pp.232-241
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• 1999

기존의 연구는 FSM을 기본으로 제어흐름만을 분석하거나 시험목적을 시험열 생성 단계에서 고려하지 않음으로써 시험열의 실제 적용에 있어 많은 문제점을 갖는다. 따라서 이 연구에서는 SDL로 기술된 프로토콜 명세서를 시멘틱 모델인 LTS로 변환 후 LTS로부터 서브투어 단위로 시험열을 생성하였다. 그리고 생성된 시험열을 TTCN으로 변환하고 단위 테스트를 위한 추가 정보로서 프리앰블, 포스트앰블, 리셋 정보등을 LTS로부터 생성하였다. 또한 LTS로부터 한 노드에서 전이 가능한 모든 경로를 트리로 표현함으로서 향상된테스트 커버리지를 갖는 서브투어를 생성하였으며 SDL을 시맨틱 모델인 STS로의변환 EH한 기존의 입력과 출력만을 고려하는 FSM에서 발생하는 비결정성 문제를 해결할 수 있다. 따라서 이 연구에서의 테스트 목적이 고려된 TTCN 표현의 테스트 케이스 생성은 적합성 시험을 위한 테스스 케이스의 실제 적용 및 프로토콜 구현의 생산성을 높일 수 있으며 테스팅 환경의 기반을 제공한다.

• Journal of Communications and Networks
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• v.10 no.3
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• pp.338-350
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• 2008

The differentiated services (DiffServ) is proposed to provide packet level service differentiations in a scalable manner. To provide an end-to-end service differentiation to users having a connection over multiple domains, as well as a flow marker, an intermediate marker is necessary at the edge routers, and it should not be operated at a flow level due to a scalability problem. Due to this operation requirement, the intermediate marker has a fairness problem among the transmission control protocol (TCP) flows since TCP flows have intrinsically unfair throughputs due to the TCP's congestion control algorithm. Moreover, it is very difficult to resolve this problem without individual flow state information such as round trip time (RTT) and sending rate of each flow. In this paper, to resolve this TCP fairness problem of an intermediate marker, we propose a fair scalable marker (FSM) as an intermediate marker which works with a source flow three color marker (sf-TCM) operating as a host source marker. The proposed fair scalable marker improves the fairness among the TCP flows with different RTTs without per-flow management. Through the simulations, we show that the FSM can improve TCP fairness as well as link utilization in multiple domain DiffServ networks.

• The KIPS Transactions:PartD
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• v.14D no.6
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• pp.633-640
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• 2007

As the embedded systems closely related with our living become complex by interoperating each other via internet, the safety issue of embedded systems begins to appear For checking safety properties of the system interactions, it is necessary to describe the system behaviors in formal methods and provide a systematic safety analysis technique. In this research, the behaviors of an embedded system are described by Labeled Transition Systems(LTS) and its safety properties are checked on the system model. For enhancing the existing compositional safety analysis technique, we perform the safety analysis techniques by checking the behavioral equivalence of the reduced model and a property model after reducing the system model in the viewpoint of the property.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.104-112
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• 1989

A design automation method for sequential circuits implementation by mans of PLA is discussed, and an optimal state-code assignment algorithm to minimize the PLA area is proposed. In order to design sequential circuit automatically, DASL (Design Automation Support Language) [8] which is easy to describe and powerful to synthesize, is proposed and used to describe sequential circuit, An optimal statecode assignment algorithm which considers next states and outputs simultaneously is proposed, and by adopting this algorithm to various examples, the area of PLA is reduced by 10% comparing privious methods. This system is constructed to design microinstruction, FSM, VLSI control part synthesis.