• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.10
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• pp.940-947
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• 2007

For the performance upgrade of a supersonic jet fighter, the processor and FLCC(Flight Control Computer) Architecture were upgraded from a baseline FLCC. Prior to the hardware implementation phase, the exact CPU throughput estimation is necessary. For this purpose, an experimental method for new FLCC throughput estimation was introduced in this study.　While baseline FLCC operating, the CPU address bus was collected with logic analyzer, and then decoded to get the exact access times to each memory-memory and the number of program Instruction branches. Based on these data, a throughput test in CPU demo-board of the new FLCC configuration was performed. From test results, the CPU-Memory architecture was design-changed before FLCC hardware implementation phase. To check the flight stability degradation due to power-interrupt problem due to CPU-Memory architecture change, the piloted HILS (Hardware-In-the Loop Simulator) test was conducted.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.10
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• pp.1081-1087
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• 2008

This paper describes limitations and solutions of the existing processor-monitoring concept for a military supersonics aircraft Flight Control Computer (FLCC) equipped with modern architecture processor to perform the system integration test. Safecritical FLCC integration test, which requires automatic test for thousands of test cases and real-time input/output test condition generation, depends on the processor-monitoring device called Processor Interface (PI). The PI, which relies upon on the FLCC processor's external address and data-bus data, has some limitations due to multi-fetching capability of the modern sophisticated military processors, like C6000's VLIW (Very-Long Instruction Word) architecture and PowerPC's Superscalar architecture. Several techniques for limitations were developed and proper monitoring approach was presented for modem processor-adopted FLCC system integration test.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.1 s.24
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• pp.89-98
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• 2006

This paper describes signal attenuation characteristics as splicing the output on LVDT for stability and reliability of switching mechanism, which is developed to use common signal between FLCC and EDFLCC, on T-50 aircraft. The method of test is classified a Pspice simulation and an actual hardware evaluation. The difference of error margin for two methods is 10times, the latter higher. The result in this experiment shows that the signal attenuation as splicing the output on LVDT doesn't affect and the static error margin is 53% for develope the EDFLCC.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.35 no.11
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• pp.1036-1042
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• 2007

It is rather difficult to improve flight control computer(FLCC) hardware(H/W) development schedule due to lack of commercial off-the-self(COTS) tools or target specific tools. Thus, it is suggested to develop an enhanced process utilizing modeling, simulation and virtual reality tools. This paper presents H/W design process enhancement tool(PET) for FLCC design requirements such as FLCC input/output(I/O) signal flow, I/O fault detection, failure management algorithm, circuit logic, PCB assembly configuration and installation utilizing simulation and visualization in virtual space. New tool will provide simulation capability of various FLCC design configuration including shop replaceable unit(SRU) level assembly/dis-assembly utilizing open flight format 3-D modeling data.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.4
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• pp.316-323
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• 2016

A UAV(Unmanned Aerial Vehicle) flies along pre-programed navigation points(in-flight, take-off, or landing) automatically without pilot input. Even though UAVs fly differently from general piloted aircraft as the pilot controls the aircraft from a ground station through means of a data-link system. Occasionally, the data-link connection can be lost for any number of reasons, in which case, the FLCC(Flight control Computer) must automatically switch to autopilot to continue flying. Hence, the FLCC is a flight-critical component that must be throughly tested and validated. This paper discusses the development of a HILS(Hardware in the Loop Simulation) test environment designed to simulate real flight conditions to verify the FLCC satisfies flying quality requirements and maintains robustness despite any potential malfunctions or emergency situations.

• Journal of Advanced Navigation Technology
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• v.25 no.4
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• pp.273-279
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• 2021

A flight control computer(FLCC) applied to an unmanned aerial vehicle(UAV) is a safety-critical item, and which is designed in a multiple structure to increase the reliability of operation by securing fault tolerance. These FLCC of multiple structure should be designed so that each independent processing/control components can perform the same operation at the same time. And for this reason, a synchronization algorithm for synchronizing the operation between FLCCs should be included in an operational flight program. In this paper, we propose a software design method for synchronization between dual FLCCs applied to UAVs. The proposed synchronization method is designed to synchronize using only the minimum hardware resources to reduce a failure rate. In addition, the proposed synchronization method is designed to minimized synchronization errors due to a timer operation by designing in consideration of operation characteristics of the hardware timer used for the synchronization.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.37 no.7
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• pp.701-708
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• 2009

The flight control law of developed flight control computer(DFLCC) is developed based on operation flight program of advanced trainer aircraft full scale development final configuration. The flight control law design is used common use development tool in GUI(Graphic User Interface) environment. The flight control law transformed to C-Code is reflected in OFP. The OFP is verified by the standardized verification process. But, before standardized verification process, we need preliminary verification process such as similarity of flight control law and reliability of developed HILS. Similarity of flight control law is verified by comparing the aircraft response of advanced trainer aircraft and those of the developed control law. Also, reliability of developed HILS is verified by comparing the aircraft response of HILS and Non-real time simulation result. This paper verifies similarity of developed control law and reliability of HILS environment as comparing aircraft response.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.7
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• pp.711-719
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• 2008

Although non-real time simulation and pilot based evaluations are available for the development of flight control computer prior to real flight tests, there are still many risky factors. The control law designed for prototype aircraft often leads to degraded performance from the initial design objectives, therefore, the proper evaluation methods should be applied such that flight control law designed can be verified in real flight environment. The one proposed in this paper is IFS(In-Flight Simulator). Currently, this system has been implemented into the F-18 HARV(High Angle of Attack Research Vehicle), SU-27 and F-16 VISTA(Variable stability. In flight Simulation Test Aircraft) programs. This paper addresses the concept of switching mechanism for FLCC(Flight Control Computer)-SWMC(Switching Mechanism Computer) using 1553B communication based on flight control law of advanced supersonic trainer. And, the fader logic of TFS(Transient Free Switch) and stand-by mode of reset '0' type are designed to reduce abrupt transient and minimize the integrator effect in pitch axis control law. It hans been turned out from the pilot evaluation in real time that the aircraft is controllable during the inter-conversion process through the flight control computer, and level 1 handling qualities are guaranteed. In addition, flight safety is maintained with an acceptable transient response during aggressive maneuver performed in severe flight conditions.