• 제목/요약/키워드: Exhaustive Test

검색결과 33건 처리시간 0.026초

Data Analysis of KOMPSAT Thermal Test in Simulated On-orbit Environment

  • Kim, Jeong-Soo;Chang, Young-Keun
    • International Journal of Aeronautical and Space Sciences
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    • 제1권2호
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    • pp.30-42
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    • 2000
  • On-orbit thermal environment test of KOMPSAT was performed in early 1999. An analysis of the test data are addressed in this paper. For the thermal-environmental simulation of spacecraft bus, an artificial heating through the radiator zones and onto some critical heat-dissipating electronic boxes was made by Absorbed-heat Flux Method. Test data obtained in terms of temperature history were reduced into flight heater duty cycles and converted into the total electrical power required for spacecraft thermal control. Verification result of flight heaters dedicated to the bus thermal control is presented. Additionally, an exhaustive heating-control process for maintaining the spacecraft thermally safe and for realistic simulation of the orbital-thermal environment during the test are graphically shown. Qualitative suggestions to post-test model correlation are given in consequency of the analysis.

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Development and Testing of a New Area Search Model with Partially Overlapping Target and Searcher Patrol Area

  • Kim, Gi-Young;Eagle, James N.;Kang, Sung-Jin
    • 한국국방경영분석학회지
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    • 제35권1호
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    • pp.21-32
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    • 2009
  • In this study, the author uses a MATLAB simulation to develop and test a generalization of the traditional Random Search model which allows both the searcher and target to move and to be in different, but overlapping, areas. Also the best evasion speed for a randomly moving target against a Systematic Search is studied.

IC 테스트 핸들러의 최적분류 알고리즘 개발 (An Optimal Sorting Algorithm for Auto IC Test Handler)

  • 김종관;최동훈
    • 대한기계학회논문집
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    • 제18권10호
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    • pp.2606-2615
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    • 1994
  • Sorting time is one of the most important issues for auto IC test handling systems. In actual system, because of too much path, reducing the computing time for finding a sorting path is the key way to enhancing the system performance. The exhaustive path search technique can not be used for real systems. This paper proposes heuristic sorting algorithm to find the minimal sorting time. The suggested algorithm is basically based on the best-first search technique and multi-level search technique. The results are close to the optimal solutions and computing time is greately reduced also. Therefore the proposed algorthm can be effectively used for real-time sorting process in auto IC test handling systems.

Testing and Self Calibration of RF Circuit using MEMS Switches

  • Kannan, Sukeshwar;Kim, Bruce;Noh, Seok-Ho;Park, Se-Hyun
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2011년도 추계학술대회
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    • pp.882-885
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    • 2011
  • This paper presents testing and self-calibration of RF circuits using MEMS switches to identify process-related defects and out of specification circuits. We have developed a novel multi-tone dither test technique where the test stimulus is generated by modulating the RF carrier signal with a multi-tone signal generated using an Arbitrary Waveform Generator (AWG) with additive white Gaussian noise. This test stimulus is provided as input to the RF circuit and peak-to-average ratio (PAR) is measured at the output. For a faulty circuit, a significant difference is observed in the value of PAR as compared to a fault-free circuit. Simulation is performed for various circuit conditions such as fault-free as well as fault-induced and their corresponding PARs are stored in the look-up table. This testing and self-calibration technique is exhaustive and efficient for present-day communication systems.

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A Hybrid Approach for Regression Testing in Interprocedural Program

  • Singh, Yogesh;Kaur, Arvinder;Suri, Bharti
    • Journal of Information Processing Systems
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    • 제6권1호
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    • pp.21-32
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    • 2010
  • Software maintenance is one of the major activities of the software development life cycle. Due to the time and cost constraint it is not possible to perform exhaustive regression testing. Thus, there is a need for a technique that selects and prioritizes the effective and important test cases so that the testing effort is reduced. In an analogous study we have proposed a new variable based algorithm that works on variables using the hybrid technique. However, in the real world the programs consist of multiple modules. Hence, in this work we propose a regression testing algorithm that works on interprocedural programs. In order to validate and analyze this technique we have used various programs. The result shows that the performance and accuracy of this technique is very high.

다중입력영역시험에서의 대형 소프트웨어 고장률 추정 연구 (Estimating the Failure Rate of a Large Scaled Software in Multiple Input Domain Testing)

  • 문숙경
    • 품질경영학회지
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    • 제30권3호
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    • pp.186-194
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    • 2002
  • In this paper we introduce formulae for estimating the failure rate of a large scaled software by using the Bayesian rule when a black-box random testing which selects an element(test case) at random with equally likely probability, is performed. A program or software can be treated as a mathematical function with a well-defined (input)domain and range. For a large scaled software, their input domains can be partitioned into multiple subdomains and exhaustive testing is not generally practical. Testing is proceeding with selecting a subdomain, and then picking a test case from within the selected subdomain. Whether or not the proportion of selecting one of the subdomains is assumed probability, we developed the formulae either case by using Bayesian rule with gamma distribution as a prior distribution.

Development of simulation-based testing environment for safety-critical software

  • Lee, Sang Hun;Lee, Seung Jun;Park, Jinkyun;Lee, Eun-chan;Kang, Hyun Gook
    • Nuclear Engineering and Technology
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    • 제50권4호
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    • pp.570-581
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    • 2018
  • Recently, a software program has been used in nuclear power plants (NPPs) to digitalize many instrumentation and control systems. To guarantee NPP safety, the reliability of the software used in safetycritical instrumentation and control systems must be quantified and verified with proper test cases and test environment. In this study, a software testing method using a simulation-based software test bed is proposed. The test bed is developed by emulating the microprocessor architecture of the programmable logic controller used in NPP safety-critical applications and capturing its behavior at each machine instruction. The effectiveness of the proposed method is demonstrated via a case study. To represent the possible states of software input and the internal variables that contribute to generating a dedicated safety signal, the software test cases are developed in consideration of the digital characteristics of the target system and the plant dynamics. The method provides a practical way to conduct exhaustive software testing, which can prove the software to be error free and minimize the uncertainty in software reliability quantification. Compared with existing testing methods, it can effectively reduce the software testing effort by emulating the programmable logic controller behavior at the machine level.

형상 추론과 기하학적 검색 기반의 다단계 경로 계획 (Multi-Stage Path Planning Based on Shape Reasoning and Geometric Search)

  • 황용구;조경래
    • 한국지능시스템학회논문지
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    • 제14권4호
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    • pp.493-498
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    • 2004
  • 전통적인 경로 계획기는 로봇의 최적 경로를 찾기 위해 광대한 기하학적 검색을 수행한다. 완전성이 있는 경로계획기는 만약 해가 존재하면 반드시 찾아야 한다. 때문에 많은 검색 시간을 소요하여 해를 찾든지, 아니면 해가 없는 경우에는 없다고 증명을 하여야 함으로 역시 많은 시간을 소요한다. 그러나 인간의 경우는 대부분의 경우에 충돌 회피 경로가 있는지 없는지 빨리 파악할 수 있는 능력을 가지고 있으며, 극단적으로 어려운 문제들을 제외하고는 무둔 경우의 수를 나열하지 않고도 쉽게 해를 찾는다. 본 연구의 목표는 이러한 인간의 사고 능력을 알고리즘화하여, 이동로봇의 운동 경로를 보다 빠르게 찾거나, 아니면 컴퓨터의 계산자원을 낭비하지 않고 일찍이 포기하게 한다. 다각형 환경과 다각형 로봇에 대한 경로계획에, 정량적인 형상 추론과 광대한 기하학적 검색을 결합한 새로운 경로 계획 방법을 제시한다. 제시되어진 알고리즘은 울타리 검증을 통해 해가 없는지를 먼저 검색하고, 만약에 해가 있으면, 정량적인 추론을 통해서 해를 찾고, 그래서 해가 존재하지만 해를 찾을 수 없으면, 완전 검색 알고리즘으로 해를 찾게 된다. 본 연구의 기여는 여러 개의 능률적인 기하학적 검사를 통해, 많은 계산량의 완전 알고리즘을 가능하면 사용하지 않고 해를 찾거나 해가 없음 증명하여, 운동 계획기의 평균 계산량을 최소화한다.

분할 및 병렬 처리 방법에 의한 BIST의 테스트 시간 감소 (Test Time Reduction for BIST by Parallel Divide-and-Conquer Method)

  • 최병구;김동욱
    • 대한전기학회논문지:시스템및제어부문D
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    • 제49권6호
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    • pp.322-329
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    • 2000
  • BIST(Built-in Self Test) has been considered as the most promising DFT(design-for-test) scheme for the present and future test strategy. The most serious problem in applying BIST(Built-in Self Test) into a large circuit is the excessive increase in test time. This paper is focused on this problem. We proposed a new BIST construction scheme which uses a parallel divide-and-conquer method. The circuit division is performed with respect to some internal nodes called test points. The test points are selected by considering the nodal connectivity of the circuit rather than the testability of each node. The test patterns are generated by only one linear feedback shift register(LFSR) and they are shared by all the divided circuits. Thus, the test for each divided circuit is performed in parallel. Test responses are collected from the test point as well as the primary outputs. Even though the divide-and-conquer scheme is used and test patterns are generated in one LFSR, the proposed scheme does not lose its pseudo-exhaustive property. We proposed a selection procedure to find the test points and it was implemented with C/C++ language. Several example circuits were applied to this procedure and the results showed that test time was reduced upto 1/2151 but the increase in the hardware overhead or the delay increase was not much high. Because the proposed scheme showed a tendency that the increasing rates in hardware overhead and delay overhead were less than that in test time reduction as the size of circuit increases, it is expected to be used efficiently for large circuits as VLSI and ULSI.

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Experimental approach to evaluate software reliability in hardware-software integrated environment

  • Seo, Jeongil;Kang, Hyun Gook;Lee, Eun-Chan;Lee, Seung Jun
    • Nuclear Engineering and Technology
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    • 제52권7호
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    • pp.1462-1470
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    • 2020
  • Reliability in safety-critical systems and equipment is of vital importance, so the probabilistic safety assessment (PSA) has been widely used for many years in the nuclear industry to address reliability in a quantitative manner. As many nuclear power plants (NPPs) become digitalized, evaluating the reliability of safety-critical software has become an emerging issue. Due to a lack of available methods, in many conventional PSA models only hardware reliability is addressed with the assumption that software reliability is perfect or very high compared to hardware reliability. This study focused on developing a new method of safety-critical software reliability quantification, derived from hardware-software integrated environment testing. Since the complexity of hardware and software interaction makes the possible number of test cases for exhaustive testing well beyond a practically achievable range, an importance-oriented testing method that assures the most efficient test coverage was developed. Application to the test of an actual NPP reactor protection system demonstrated the applicability of the developed method and provided insight into complex software-based system reliability.