• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.205-212
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• 2017

Linux Foundation has announced a real-time kernel, called Zephyr, for IoT applications recently. Zephyr kernel provides synchronous and asynchronous IPC for data communication between threads. Synchronous IPC is useful for programming multi-threads that need to be executed synchronously, since the sender thread is blocked until the data is delivered to the receiver thread and the completion of data transfer can be known to two threads. In general, 'IPC execution time' is defined as the time duration between the sender thread sends data and the receiver thread receives the data sent. Especially, it is important that 'IPC execution time' in the synchronous IPC should be fixed in real-time kernel like Zephyr. However, we have found that the execution time of the synchronous IPC in Zephyr kernel increases in proportion to the number of threads executing in the kernel. In this paper, we propose a method to implement a fixed time synchronous IPC in Zephyr kernel using Direct Thread Switching(DTS) technique. Using the technique, the receiver thread executes directly after the sender thread sends a data during the remaining time slice of the sender thread and we can archive a fixed IPC execution time even when the number of threads executing in the kernel increases. In this paper, we implemented synchronous IPC using DTS in the Zephyr kernel and found the IPC execution time of the IPC is always 389 cycle that is relatively small and fixed.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.3
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• pp.127-137
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• 2010

As large-scale computational applications in various scientific domains have been utilized over many integrated sets of grid computing resources, the difficulty of their execution management and control has been increased. It is beneficial to refer job history generated from many application executions, in order to identify application‘s characteristics and to decide selection policies of grid resource meaningfully. In this paper, we apply a statistical technique, Plackett-Burman design with fold-over (PBDF), for analyzing grid environments and execution history of applications. PBDF design identifies main factors in grid environments and applications, ranks based on how much they affect to their execution time. The effective factors are used for selecting reference job profiles and then preferable resource based on the reference profiles is chosen. An application is performed on the selected resource and its execution result is added to job history. Factor's credit is adjusted according to the actual execution time. For a proof-of-concept, we analyzed job history from an aerospace research grid system to get characteristics of grid resource and applications. We built JARS algorithm and simulated the algorithm with the analyzed job history. The simulation result shows good reliability and considerable performance in grid environment with frequently crashed resources.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.6
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• pp.133-137
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• 2018

Arduino is a small microcomputer that is used in a variety of industry fields and especially is widely used as an open source hardware IoT device. The multi-tasking method of Arduino is divided into super loop timing and RTOS thread method. The super loop timing method is simple and easy to understand. However, when one task is long, it affects the execution of the next task. In addition, RTOS threading has the advantage of being able to run without being influenced by other work time. However, Arduino, a small microcomputer, has a disadvantage in that, when the number of threads increases, the context switching time of the thread causes additional time not included in the super loop timing method have. In this paper, we use Arduino Uno R3 and FreeRTOS to analyze these different features, and the task for the experiment is to send 8000 digital signals to the built-in LED port. If two tasks of the same size are executed, the super loop method executes 3 ms faster than FreeRTOS multitasking. If multiple tasks are executed simultaneously, superloop type task is sequential execution and difference in execution time between first task and last task is large. FreeRTOS method can be executed concurrently, but execution time delay of about 30 ms occurs in context switching time.

• Journal of Institute of Control, Robotics and Systems
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• v.17 no.11
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• pp.1074-1081
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• 2011

As robotics systems are becoming more complex there is the need to promote component based robot development, where systems can be constructed as the composition and integration of reusable building block. One of the most important challenges facing component based robot development is safeguarding against software component failures and malfunctions. The health monitoring of the robot software is most fundamental factors not only to manage system at runtime but also to analysis information of software component in design phase of the robot application. And also as a lot of monitoring events are occurred during the execution of the robot software components, a simple data treatment and efficient memory management method is required. In this paper, we propose an efficient events monitoring and data management method by modeling robot software component and monitoring factors based on robot software framework. The monitoring factors, such as component execution runtime exception, Input/Output data, execution time, checkpoint-rollback are deduced and the detail monitoring events are defined. Furthermore, we define event record and monitor record pool suitable for robot software components and propose a efficient data management method. To verify the effectiveness and usefulness of the proposed approach, a monitoring module and user interface has been implemented using OPRoS robot software framework. The proposed monitoring module can be used as monitoring tool to analysis the software components in robot design phase and plugged into self-healing system to monitor the system health status at runtime in robot systems.

• The KIPS Transactions:PartD
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• v.12D no.2 s.98
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• pp.283-288
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• 2005

Test case prioritization methods schedule test cases for execution when we can not practically run all test cases for regression testing. We proposed a new prioritization method that is based on historical execution and mr detection data. And we conducted an experiment to compare the proposed method with existing Random and LRU methods using the fault age under the long run environment as criterion. The experiment shows several interesting results. First, our results show that they are complementary. Random method shows good performance for programs that have many error-detectable test cases and HED is more effective for the programs that can be detected by very small amount of test cases. But LRU is more effective for the programs that have relatively medium amount of error detectable test cases. Next, the performance of prioritization method is affected by the size of test suites. Two experiments that have different size of test suites show considerably different fault ages and performance order. And lastly, the $20\%$ of test cases shows considerably good performance compared to the execution result of the full test suite.

• Journal of the Korea Society of Computer and Information
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• v.17 no.7
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• pp.87-95
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• 2012

In this paper, PTAS three-dimensional Steiner minimum tree connecting numerous input nodes rapidly in 3D space is proposed. Steiner minimum tree problem belongs to NP problem domain, and when properly devised heuristic introduces, it is generally superior to other algorithms as minimum spanning tree affiliated with P problem domain. But when the number of input nodes is very large, the problem requires excessive execution time. In this paper, a method using PTAS is proposed to solve the difficulty. In experiments for 70,000 input nodes in 3D space, the tree produced by the proposed 8 space partitioned PTAS method reduced 86.88% execution time, compared with the tree by naive 3D steiner minimum tree method, though increased 0.81% tree length. This affirms the proposed method can work well for applications that many nodes of three dimensions are need to connect swifty, enduring slight increase of tree length.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.5
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• pp.309-318
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• 1987

In the on-line security analysis of power system, Automatic Contingency Selection (ACS) is commonly used to reduce the number of contingency cases which will be evaluated in detail. This paper describes a fast and reliable ACS method which adopts DC load flow in conjunction with compensation theorem to improve execution time, and applies severity performance index, divided on each limit level for considering overload rate, to make reliable contingency ranking. The method has been tested in IEEE 25 bus system and KEPCO 130 bus actual power system. The results of these tests verify its superiority to both the execution time and reliability, and illustrate its effectiveness for the practical use.

• Journal of the Korea Computer Industry Society
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• v.8 no.3
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• pp.167-172
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• 2007

Generally, In a application program the core part for parallel processing is a loop. therefore in this paper, loop interchange parallel compiler is proposed. this is a procedure for the automatic conversion of a loop interchange. According to execution to the outside CDOALL statements of cedar fortran, loop interchange is more effectively method the extracting parallelism in order to parallel processing in iterations. This method will be expected to effectively execution result with mixed into linear conversion and go far toward solving the effectively implementation of the non-unimodular nested loop.

• Magazine of the Korean Society of Agricultural Engineers
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• v.13 no.1
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• pp.2158-2161
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• 1971

Although underdrainage has been studied for a long time, it is the third attempt in korea to execute, using P. V. C.(plastic) suction pipes in the low and wet fields. First, three execution plots and three control plots were set, then the drainage method and volume, soil temperature, growth and yield of crops, and under ground water level in the execution plot have been examined. These experiments have conducted with No-ngnim No 6(rice), and Palgweng (rice) which are the recommended varieties. And the above experiments have been executed for seven months between January and July. 1970. The experimenntal method adopted and the results obtained through the exeperiments are as follows:

• Journal of information and communication convergence engineering
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• v.7 no.4
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• pp.516-520
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• 2009

RSA crypto-processors equipped with more than 1024 bits of key space handle the entire key stream in units of blocks. The RSA processor which will be the target design in this paper defines the length of the basic word as 128 bits, and uses an 256-bits register as the accumulator. For efficient execution of 128-bit multiplication, 32b*32b multiplier was designed and adopted and the results are stored in 8 separate 128-bit registers according to the status flag. In this paper, an efficient method to execute 128-bit MAC (multiplication and accumulation) operation is proposed. The suggested method pre-analyzed the all possible cases so that the MAC unit can remove unnecessary calculations to speed up the execution. The proposed architecture prototype of the MAC unit was automatically synthesized, and successfully operated at 20MHz, which will be the operation frequency in the RSA processor.