• 대한전자공학회논문지
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• 제27권10호
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• pp.106-112
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• 1990

다공질 실리콘을 열산화할 때 산화의 온도 의존성과 IR흡수 스펙트럼을 조사하여 다공질 실리콘외 산화특성을 조사하였다. PSL(porous silicon layer)을 $700^{\circ}C$에서 1시간, $1100^{\circ}C$에서 1시간으로 2단계 습식산화시켜 bulk 실리콘의 열산화막과 같은 성질의 수십 ${\mu}m$두께의 OPSL(oxidized porous silicon layer)을 짧은 시간에 형성시킬 수 있으며, 식각율과 항복전계는 산화온도와 산화 분위기에 크게 의존하는 것으로 나타났다. 이때 PSL의 산화율은 약 390nm/s이고, 항복전계는 1.0MV/cm~2.0MV/cm의 분포를 갖는다. 웨이퍼 휨을 측정하여 고온 열산화시 발생하는 산화막의 stress를 조사하였다. $1000^{\circ}C$ 이상의 고온에서 건식산화할 경우 발생하는 stress는 ${10^2}dyne/{cm^2}~{10^10}dyne/{cm^2}$로 측정되었다.

• 전자공학회논문지D
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• 제36D권5호
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• pp.21-28
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• 1999

Deep Submicron 영역에서 요구되는 고성능 소자로서 자기-정렬된 ESD(Elevated Source/Drain)구조의 MOSFET을 제안하였다. 제안된 ESD 구조는 일반적인 LDD(Lightly-Doped Drain)구조와는 달리 한번의 소오스/드레인 이온주입 과정이 필요하며, 건식 식각 방법을 적용하여 채널의 함몰 깊이를 조정할 수 있는 구조를 갖는다. 또한 제거가 가능한 질화막 측벽을 최종 질화막 측벽의 형성 이전에 선택적인 채널 이온주입을 위한 마스크로 활용하여 hot-carrier 현상을 감소시켰으며, 반전된 질화막 측벽을 사용하여 기존이 ESD 구조에서 문제시될 수 있는 자기-정렬의 문제를 해결하였다. 시뮬레이션 결과, 채널의 함몰 깊이 및 측벽의 넓이를 조정함으로써 충격이온화율(ⅠSUB/ID) 및 DIBL(Drain Induced Barrier Lowering) 현상을 효과적으로 감소시킬 수 있고, 유효채널 길이에 따라 차이가 있으나 두 번의 질화막 측벽을 사용함으로써 hot-carrier 현상이 개선될 수 있음을 확인하였다.

• 한국산업보건학회지
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• 제3권2호
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• pp.152-165
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• 1993

This study was performed at eleven small-sized plating factories located in Seoul, Incheon, Ansan, and Taejeon from July 21 to October 6, 1992. The major objectives of this study were to evaluate worker exposure to hexavalent chromium and local exhaust ventilation (L.E.V.) systems at the chromium plating operations. The most suitable L.E.V. systems for chromium plating tanks were designed as examples for recommendation to the industry. The results are summarized as follows. The range of chromium plating operations investigated included decorative, hard, and black chromium plating on several kinds of parts. Most of plating tanks were not equipped with proper control methods against emission of hexavalent chromium mists and workers were not wearing appropriate personal protectives. The ariborne hexavalent chromium concentrations showed an approximate lognormal distribution. The geometric means of both personal and area samples were within the Korean and ACGIH standards, $50{\mu}g/m^3$. However, in comparison with the NIOSH criterion, $1{\mu}g/m^3$, the geometric means of personal samples at two factories and the geometric means of area samples at two factories exceeded it. The geometric means of personal and area samples of high exposure groups (above the NIOSH criterion) were 7 and 27 times higher than those of low exposure groups (below the NIOSH criterion), respectively. The L.E.V. systems of high exposure groups were improperly designed, and the factory with the highest exposure level had no L.E.V. systems at all on chemical etching process. Whereas at factories of low exposure groups, mist control methods such as mist suppressants, tank cover, and/or auxillary L.E.V. systems were added to L.E.V systems. The evaluation of L.E.V. systems showed that there was no chromium plating operation satisfying the ACGIH criteria for capture velocity, slot velocity, and exhaust rate simultaneously. To increase performance of L.E.V. systems, it must be designed to minimize the impact of boundary layer separation. Push-pull ventilation hood and downward plenum ventilation hood were suggested for the Korean industry.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 춘계학술대회 논문집
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• pp.1051-1054
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• 2000

We developed the micro CSF (celebrospinal fluid) shunt valve with surface and bulk micromachining technology in polymer MEMS. This micro CSF shunt valve was formed with four micro check valves to have a membrane connected to the anchor with the four bridges. The up-down movement of the membrane made the CSF on & off and the valve characteristic such as open pressure was controlled by the thickness and shape of the bridge and the membrane. The membrane, anchor and bridge layer were made of the $O_2$ RIE (reactive ion etching) patterned Parylene thin film to be about 5~10 microns in thickness on the silicon wafer. The dimension of the rectangular nozzle is 0.2＊0.2 $\textrm{mm}^2$ and the membrane 0.45 mm in diameter. The bridge width is designed variously from 0.04 mm to 0.12 mm to control the valve characteristics. To protect the membrane and bridge in the CSF flow, we developed the packaging system for the CSF micro shunt valve with the deep RIE of the silicon wafer. Using this package, we can control the gap size between the membrane and the nozzle, and protect the bridge not to be broken in the flow. The total dimension of the assembled system is 2.5＊2.5 $\textrm{mm}^2$ in square, 0.8 mm in height. We could precisely control the burst pressure and low rate of the valve varing the design parameters, and develop the whole CSF shunt system using this polymer MEMS fabricated CSF shunt valve.

• 한국전기전자재료학회논문지
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• 제26권5호
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• pp.335-340
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• 2013

In this study, the plasma etching of the TaN thin film with $CH_4/BCl_3/Ar$ gas chemistries was investigated. The etch rate of the TaN thin film and the etch selectivity of TaN to $SiO_2$ was studied as a function of the process parameters, including the amount of $CH_4$. X-ray photoelectron spectroscopy (XPS) and Field-emission scanning electron microscopy (FE-SEM) was used to investigate the chemical states of the surface of the TaN thin film.

• 한국재료학회지
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• 제9권5호
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• pp.503-508
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• 1999

We have investigated the physical and diffusion barrier property of Ti-Si-N film for Cu metallization. The ternary compound was deposited by using reactive rf magnetron sputtering of a TiSi$_2$target in an Ar/$N_2$gas mixture. Resistivities of the films were in range of 358$\mu$$\Omega$-cm, to 307941$\mu$$\Omega$-cm, and tended to increase with increasing the $N_2$/Ar flow rate ratio. The crystallization of the Ti-Si-N compound started to occur at 100$0^{\circ}C$ with the phases of TiN and Si$_3$N$_4$identified by using XRD(X-ray Diffractometer). The degree of the crystallization was influenced by the $N_2$/Ar flow ratio. The diffusion barrier property of Ti-Si-N film for Cu metallization was determined by AES, XRD and etch pit by secco etching, revealing the failure temperature of 90$0^{\circ}C$ in 43~45at% of nitrogen content. In addition, the very thin compound (10nm) with 43~45at% nitrogen content remained stable up to $700^{\circ}C$. Furthermore, thermal treatment in vacuum at $600^{\circ}C$ improved the barrier property of the Ti-Si-N film deposited at the $N_2$(Ar+$N_2$) ratio of 0.05. The addition of Ti interlayer between Ti-Si-N films caused the drastic decrease of the resistivity with slight degradation of diffusion barrier properties of the compound.

• Korean Chemical Engineering Research
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• 제54권4호
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• pp.459-464
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• 2016

본 연구에서는 리튬이온 전지용 실리콘 음극소재의 사이클 안정성 및 율속 특성 향상을 위해 다공성 실리콘/탄소 복합소재의 전기화학적 특성을 조사하였다. 나노 실리카 제조는 스토버 방법을 사용하고 교반 속도, 교반 온도 및 $NH_3$/TEOS 비율을 조절 하여 100~500 nm 크기의 구형 실리카를 합성하였다. 구형 나노 실리카의 마그네슘 열환원과 산처리 과정을 통해 다공성 실리콘을 얻고, 제조된 다공성 실리콘에 Phenolic resin을 탄소전구체로 사용하여 최종적으로 다공성 실리콘/탄소 활물질을 합성하였다. 또한 $LiPF_6$ (EC:DMC:EMC=1:1:1 vol%) 전해액에서 다공성 실리콘/탄소 음극소재의 충 방전, 순환전압 전류, 임피던스 테스트 등의 전기화학적 특성을 조사 하였다. 다공성 실리콘/탄소 복합소재의 음극활물질로서 코인 전지의 성능을 조사한 결과 초기용량 및 40사이클 용량 보존율은 각각 2,006 mAh/g, 55.4%를 나타내었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.863-866
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• 1999

(Ba,Sr)$TiO_3$ thin films have attracted groat interest as new dielectric materials of capacitors for ultra-large-scale integrated dynamic random access memories (ULSI-DRAMs) such as 1 Gbit or 4 Gbit. In this study, inductively coupled $BCl_3/Cl_2$/Ar plasmas was used to etch (Ba,Sr)$TiO_3$ thin films. RF power/dc bias voltage = 600 W/-250 V and chamber pressure was 10 mTorr. The $Cl_2/(Cl_2+Ar)$ was fixed at 0.2, the (Ba,Sr)$TiO_3$ thin films were etched adding $BCl_3$. The highest (Ba,Sr)$TiO_3$ etch rate is 480$\AA/min$ at 10 % $BCl_3$ adding to $Cl_2$/Ar. The characteristics of the plasmas were estimated using optical emission spectroscopy (OES). The change of Cl, B radical density measured by OES as a function of $BCl_3$ percentage in $Cl_2$/Ar. The highest Cl radical density was shown at the addition of 10% $BCl_3$ to $Cl_2$/Ar. To study on the surface reaction of (Ba,Sr)$TiO_3$ thin films was investigated by XPS analysis. Ion enhancement etching is necessary to break Ba-O bond and to remove $BaCl_2$. There is a little chemical reaction between Sr and Cl, but Sr is removed by physical sputtering. There is a chemical reaction between Ti and Cl, and Tic14 is removed with ease. The cross-sectional of (Ba,Sr)$TiO_3$ thin film was investigated by scanning electron microscopy (SEM), the etch slope is about $65\;{\sim}\;70$.

• 멤브레인
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• 제28권3호
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• pp.169-179
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• 2018

본 연구는 역삼투막의 물리-화학적 표면 개질을 통하여 친수성 증가에 따른 내오염성 및 내염소성을 향상하고자 하였다. 자외선조사로 상용막 표면을 활성화한 후 실란 커플링제를 sol-gel법으로 개질하여 염소에 대한 민감도를 낮춰 폴리아마이드 활성층을 보호하여 내염소성을 향상시켰다. 또한, 에폭사이드의 개수가 다른 PGPE, SPE 두 종류의 에폭시로 코팅 후 에폭사이드의 개환반응으로 내오염성을 향상시켰으며, 표면 개질 조건은 접촉각과 FT-IR, XPS 분석을 통해 최적화하였다. 실란-에폭시 개질막의 오염성 평가 결과 투과도 감소율이 상용막보다 약 1.5배 감소하였고, 내염소성 평가 결과 $20,000ppm{\times}hr$에서도 염제거율이 90% 이상 유지되었다.

• 센서학회지
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• 제22권2호
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• pp.130-135
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• 2013

This study proposed a noble process to fabricate TSV (Through Silicon Via) structure which has lower cost, shorter production time, and more simple fabrication process than plating method. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process. The via hole was $100{\mu}m$ in diameter and $400{\mu}m$ in depth. A dielectric layer of $SiO_2$ was formed by thermal oxidation on the front side wafer and via hole side wall. An adhesion layer of Ti and a seed layer of Au were deposited. Soldering process was applied to fill the via holes with solder paste and metal powder. When the solder paste was used as via hole metal line, sintering state and electrical properties were excellent. However, electrical connection was poor due to occurrence of many voids. In the case of metal powder, voids were reduced but sintering state and electrical properties were bad. We tried the via hole filling process by using mixing solder paste and metal powder. As a consequence, it was confirmed that mixing rate of solder paste (4) : metal powder (3) was excellent electrical characteristics.