• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.411-414
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• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PT layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PT layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PT layer of c-axial orientation rained thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PT layer were measured, too.

• Journal of the Korean institute of surface engineering
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• v.29 no.1
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• pp.60-72
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• 1996

A photoetching process is widely used for small and high precision parts in machinery, electronic and semi-conductor industries. One of the high precision parts, grid is very important part of digitron which use electron display, and it is fabricated by only photoetching process because of high precision. In this study, to develop high precision digitron grid, characteristics of etching solution were investigated with electrochemical test, that was potentiodynamic test and immersion test in the ferric chloride solution and added some additives. Based on the electrochemical etching test, grid was fabricated by continuous photoetching process at various etching condition. From the result of measured line width and etching depth under-cut and etching factor were calculated. For the fabrication of 25$\mu\textrm{m}$ line width, optimal etching condition was etching temperature 40~$45^{\circ}C$, spray pressure 1.5kg/$\textrm{cm}^2$ and etching time 3~4min.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.18 no.2
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• pp.38-43
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• 2019

Electrochemical etching is a popular process to apply metal patterning in various industries. In this study, the electrochemical etching using a patterned copper layer was proposed to fabricate multilayered structures. The process consists of electrodeposition, laser patterning, and electrochemical etching, and a repetition of this process enables the production of multilayered structures. In the fabrication of a multilayered structure, an etch factor that reflects the etched depth and pattern size should be considered. Hence, the etch factor in the electrochemical etching process using the copper layer was calculated. After the repetition process of electrochemical etching using copper layers, the surface characteristics of the workpiece were analyzed by EDS analysis and surface profilometer. As a result, multilayered structures with various shapes were successfully fabricated via electrochemical etching using copper layers.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.65-66
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• 2005

Etching characteristics of $Ge_2Sb_2Te_5$ (GST) films were investigated using $Cl_2$/Ar inductively coupled plasma.We examined the etching characteristics such as etching rate and selectivity over oxide films of GST films using inductively coupled plasma (ICP) with various etching parameters such as $Cl_2$/Ar gas mixing ratios, ICP source power, pressure, and bias power. The maximum etch rate of GST film was $2,815{\AA}$/min and the selectivity higher than 12:1 over the oxide films was also obtained at the $Cl_2$ flow rates of 40 sccm.

• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2501-2503
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• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PTO layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PTO layer of c-axial orientation raised thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PTO layer were measured, too.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.259-262
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• 2003

Superconducting flux flow transistor(SFFT) is based on a control of the Abrikosov vortex flowing along a channel. The induced voltage by moving of the Abrikosov vortex in SFFT is greatly affected by the thickness and width, of channel. In order to fabricate a reproducibility channel in SFFT, we have researched the variation of the critical characteristics of YBCO thin films with the etching time using ICP(Inductively coupled plasma) system. It was certified that the velocity of vortex decreased with increasing the width of channel and was saturated faster in low bias from a simulation. An etching mechanism of YBCO thin films by ICP system was also certified by AFM(Atomic Force Microscope) and by measuring the critical current density with etching time. As measurement result, we could analyze that we should optimize the etching thickness of channel part to construct a flux flow transistor with desired characteristics.

• Journal of the Korean Vacuum Society
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• v.8 no.4A
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• pp.476-481
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• 1999

Characteristics of platinum dry etching were investigated in a cryogenic magnetized inductively coupled plasma (MICP). The problem with platinum etching is the redeposition of sputtered platinum on the sidewall. Because of the redeposits on the sidewall, the etching of patterned platinum structure produces feature sizes that exceed the original dimension of the PR size and the etch profile has needle-like shape [1]. The main object of this study was to investigate a new process technology for fence-free Pt etching As bias voltage increased, the height of fence was reduced. In cryogenic etching, the height of fence was reduced to 20% at-$190^{\circ}C$ compared with that of room temperature, however the etch profile was not still fence-free. In Ar/$SF_6$ Plasma, fence-free Pt etching was possible. As the ratio of $SF_6$ gas flow is more than 14% of total gas flow, the etch profile had no fence. Chemical reaction seemed to take place in the etch process.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.41-46
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• 2006

Wet etching process in recent semiconductor manufacturing is devided into batch and single wafer type. Batch type wet etching process provides more throughput with poor etching uniformity compared to single wafer type process. Single wafer process achieves better etching uniformity by boom-swing injected chemical on rotating wafer. In this study, etching characteristics of $SiO_2$ layer at room and elevated temperature is evaluated and compared. The difference in etching rate and uniformity of each condition is identified, and the temperature profile of injected chemical is theoretically calculated and compared to that of experimental result. Better etching uniformity is observed with single wafer tool with boom-swing injection compared to single wafer process without boom-swing or batch type tool.

• Journal of the Semiconductor & Display Technology
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• v.8 no.4
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• pp.1-5
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• 2009

This investigation is applied Taguchi method and the analysis of variance(ANOVA) to the reactive ion etching(RIE) characteristics of $SiO_2$ film coated on a wafer with Experimental Analysis and Optimization of $CF_4/O_2$ Plasma Etching Process mixture. Plans of experiments via nine experimental runs are based on the orthogonal arrays. A $L_9$ orthogonal array was selected with factors and three levels. The three factors included etching time, RF power, gas mixture ratio. The etching rate of the film were measured as a function of those factors. In this study, the etching thickness mean and uniformity of thickness of the RIE are adopted as the quality targets of the RIE etching process. The partial factorial design of the Taguchi method provides an economical and systematic method for determining the applicable process parameters. The RIE are found to be the most significant factors in both the thickness mean and the uniformity of thickness for a RIE etching process.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.249-255
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• 2002

For a formation of membrane structures, single crystal silicon wafers have been anisotropically etched with solutions of KOH and KOH-IPA. The etching rate was observed to be strongly dependent upon the etchant temperature and concentration. Mask patterns for the etching experiment was aligned to incline $45^{\circ}$on the primary flat of the silicon wafer. The different etching characteristics were observed according to pattern directions and etchant concentration. When the KOH concentration was fixed to 20 wt%, the U-groove etching shape was observed for the etching temperature of above $80^{\circ}C$, and V-groove shapes observed at below $80^{\circ}C$. Hillocks, which were generated at the etched silicon surfaces, has been decreased as the increasing of the etchant temperature and concentration.