• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1342-1348
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• 1998

The major limitation of MOM solution has alaways been the computer CPU time and storage size, needed to carry out the impedance matrix computation. A new formulation technique using Sorce Superimposion method is presented in order to cut down computerstorage requirements and CPU time based on the equivalence principle and induction theorem. The numerical results are shown to give good agreement to those calculated by the conventional method and also application example is presented.

• Korean Institute of Interior Design Journal
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• v.13 no.3
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• pp.76-83
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• 2004

Nowadays, our societies use digital technology in new architectural shape and space design to transcend three dimension limit so the boundary of the imagination world and actuality world has been collapsed. Traditional spatial value has been collapsed. Also indetermination and temporary assumption in time, fluidness and dematerialized, simultaneity and reiteration in image are relative with this circumstances. In architectural shape, media characteristics which secede from traditional characteristics of place tectonic value have occurred. Therefore, indifference and interests in shape, inter-permeation in interior and exterior space, homogeneous equivalence spatial extension have occurred. The purpose in this study examines dematerialized in contemporary space design and light materials and also investigates general and architectural background. The results of this study are as follows. First, circumstances of human have changed from physically limited boundary to unfixed, nonphysical, lightness and vague things. Second, casting off volume in shape and also dissembling exclusive and constructive Third, interior and exterior space by transparency intimates media possibility of information screen. Fourth, seek information and organic response, ambivalent transformation, accumulation of image and new mutual understanding system.

• Proceedings of the Korean Information Science Society Conference
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• 2008.06b
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• pp.568-571
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• 2008

하드웨어 개발에 있어서 데이터의 신속한 처리와 공정의 저렴한 비용을 위해 회로의 많은 부분이 게이트 레벨에서 구현된다. 기능 검사는 하드웨어 개발에 있어서 설계의 기능을 분석하는 중요한 설계 흐름이다. 기존의 기능 검사는 사용자의 요구에 의해 하드웨어 시스템이 복잡해지고 개발 주기가 점점 빨라지는 시장의 특성으로 인해 설계자에게 시간적 경제적인 부담감을 준다. 본 연구에서는 설계자에게 가중되는 부담을 극복하고 보다 효율적인 기능 검사를 위해 모델 체킹을 동치성 검사에 적용하는 방법을 제안하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.6 s.324
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• pp.87-92
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• 2004

Several stubs are added to a rectangular slot for giving an improvement in both return loss and isolation for a slot-coupled microstrip directional coupler. Its closed-form design equations are derived by velocity equalization of two normal modes and network equivalence. It was verified that nearly ideal performance is achievable by design examples.

• Journal of the Korean Data and Information Science Society
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• v.24 no.6
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• pp.1503-1520
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• 2013

For multi-line insurance companies, allocating the risk capital to each line is a widely-accepted risk management exercise. In this article we consider several applications of the Euler capital allocation. First, we propose visual tools to present the diversification and the line-wise performance for a given loss portfolio so that the risk managers can understand the interactions among the lines. Secondly, on theoretical side, we prove that the Euler allocation is the directional derivative of the marginal or incremental allocation method, an alternative capital allocation rule in the literature. Lastly, we establish the equivalence between the mean-shortfall optimization and the RORAC optimization when the risk adjusted capital is the expected shortfall, and show how to construct the optimal insurance business mix that maximizes the portfolio RORAC. An actual loss sample of an insurance portfolio is used for numerical illustrations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.6
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• pp.22-25
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• 2010

This paper presents the modified design that can reject the harmonic signals in the branch-line coupler. After adding open stubs at the center of quarter-wavelength lines of the traditional design, all network parameters can be determined by network equivalence, in order to maintain the conventional function at the operating frequency and suppress its harmonic terms to de chosen. Experimental results show the second and third harmonic suppressions to be -37.5 and -42.7dBs, while maintaining conventional performance at the fundamental frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1842-1849
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• 1996

This paper presents a full-wave, moment method analysis of a Moreno directional coupler with tow crossed-slots between two crossed rectangular waveguides. the overall structure is divided into several rectangular waveguides and cavities by the use of the equivalence principle to the complex slot regions. this enables a simple and efficient analysis involving the well-known retangular waveguide/cavity Green's functions. For a numerically efficient simulation, the roof-top basis expansion and line testing is used and an acceleration technique is applied to the series summation in the Green's functions. The numerical results are compared with the measurements to verify the correctness of the present analysis.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06b
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• pp.354-357
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• 2007

하드웨어 개발에 있어서 데이터의 신속한 처리와 공정의 저렴한 비용을 위해 회로의 많은 부분이 게이트 레벨에서 구현된다. 기능 검사는 하드웨어 개발에 있어서 설계의 기능을 분석하는 중요한 설계 흐름이다. 기존의 기능 검사는 사용자의 요구에 의해 하드웨어 시스템이 복잡해지고 개발 주기가 점점 빨라지는 시장의 특성으로 인해 설계자에게 시간적 경제적인 부담감을 준다. 본 연구에서는 설계자에게 가중되는 부담을 극복하고 보다 효율적인 기능 검사를 위해 모델 체킹을 동치성 검사에 적용하는 방법을 제안하고자 한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.1133-1138
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• 2000

최소비용 선형 망 흐름 문제가 동등한 할당 문제로 변환될 수 있으며, 또한 선형 망 흐름 문제를 해결하기 위한 전통적 방법은 단순 싸이클 흐름을 변환시킴으로서 원시 비용을 개선하는 방법이다. Auction 알고리즘이 각각의 반복에서 분산계산을 제시하는 개체와 초기의 대상 가격을 선택하기 위하여 몇 개의 특별한 법칙과 함께 동일한 문제에 적용이 될 때, 개체는 ${\varepsilon}$-이완법의 형태에서 획득할 수 있다. 본 논문은 할당 문제를 해결하기 위한 방법으로 최소비용 흐름 문제를 일반화 시켜, 전형적인 반복에 최소비용 흐름 문제, 수학적 등가에 의한 최소비용 흐름 문제를 연구하였고, 최소비용 흐름 측면에서 수송문제의 확장과 ${\varepsilon}$-이완법을 도출하여 이를 PCB 설계에 응용하고자 하였다.

• Journal of the Korea Society of Computer and Information
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• v.24 no.2
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• pp.57-66
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• 2019

This paper compared the performance with an overview of channel equalization techniques used in high-speed serial transceivers, including the homogeneous architecture and associated components for the GHz interconnect of backplane and cable channels. It also used the MATLAB tool to present system analysis and simulation results for continuous time equivalent structures. In the case of conventional continuous equalization, high frequency deficits occur due to the use of a comparator that is difficult to implement as well as the low speed limit. In this paper, the channel equalization technique based on the power spectrum analysis of clocks was used to compensate for the frequency loss, and the application of the TX+Channel and TX+Equalizer filters enabled the measurement of attenuation and equivalence without comparators. The application of blender and band-pass filters at high speeds also showed significant effectiveness.