• 전기전자학회논문지
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• 제18권2호
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• pp.228-233
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• 2014

In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.

• Journal of Communications and Networks
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• 제16권1호
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• pp.36-44
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• 2014

Exploiting the energy-delay tradeoff for energy saving is critical for developing green wireless communication systems. In this paper, we investigate the delay-constrained energy-efficient packet transmission. We aim to minimize the energy consumption of multiple randomly arrived packets in an additive white Gaussian noise channel subject to individual packet delay constraints, by taking into account the practical on-off circuit power consumption at the transmitter. First, we consider the offline case, by assuming that the full packet arrival information is known a priori at the transmitter, and formulate the energy minimization problem as a non-convex optimization problem. By exploiting the specific problem structure, we propose an efficient scheduling algorithm to obtain the globally optimal solution. It is shown that the optimal solution consists of two types of scheduling intervals, namely "selected-off" and "always-on" intervals, which correspond to bits-per-joule energy efficiency maximization and "lazy scheduling" rate allocation, respectively. Next, we consider the practical online case where only causal packet arrival information is available. Inspired by the optimal offline solution, we propose a new online scheme. It is shown by simulations that the proposed online scheme has a comparable performance with the optimal offline one and outperforms the design without considering on-off circuit power as well as the other heuristically designed online schemes.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 추계학술대회 논문집
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• pp.159-163
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• 2001

A new and high-efficient energy-recovery circuit is proposed to drive a Plasma display panel (PDP) and compared with the conventional circuit. The Proposed circuit uses only two inductors and no auxiliary circuit to recover the energy stored in the equivalent intrinsic capacitance of Plow DP so that it feartures a very simple structure, small volume, fewer power devices. production cost and high efficiency. Besides, the light emitted from PDP is very stable and uniform. It is suitable for wall-hanging color TVs. The proposed circuit, operating at 200kHz, is verified to be applicable on a 42-inch PDP by an experiment.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.169-172
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• 2008

This paper is a report of designing for high efficient LED lights driver. The main purpose of driver designing is meet the requirement the high efficient energy regulation for light of Korea. To meet the regulation the high efficient, the circuit adapted wide range resonant power supply and current regulate circuit to adjust LED current. This product archived excellent performance as well as reliable operation.

• 전기전자학회논문지
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• 제23권3호
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• pp.878-882
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• 2019

XOR(exclusive-OR)-XNOR(exclusive NOR) 회로는 고 성능 산술 연산에 필요한 4-2 압축 회로(4-2 compressor)의 기본 구성 요소이다. 본 논문에서는 에너지 효율이 우수한 XOR-XNOR 회로를 제안한다. 제안한 회로는 임계 경로의 내부 기생 캐패시턴스를 감소시켜 전파 지연 시간을 감소시켰으며, 모든 입력 조합의 경우에 완벽한 출력 값을 가지며 8개의 트랜지스터로 설계되었다. 기존 회로와 비교하여 제안한 회로는 전파 지연 시간이 14.5% 감소하였으며, 전력 소모는 1.7% 증가하였다. 따라서 전력 소모와 지연 시간의 곱 (power-delay product: PDP)과 에너지와 지연 시간의 곱 (energy-delay product: EDP) 각각 13.1%, 26.0% 감소하였다. 제안한 회로는 0.18um CMOS 표준공정을 이용하여 설계하였으며 SPICE 시뮬레이션을 통해 타당성을 입증하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.505-508
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• 2000

A coreless printed circuit board(PCB) transformer is employed in a contactless energy transfer circuit that achieves an efficient power conversion at the presence of a considerable airgap between the source and the load side. A half-bridge series resonant converter is selected as the contactless energy transfer circuit in order to minimize the detrimental effects of large leakage inductance small magnetizing inductance and poor coupling coefficient of the coreless PCB transformer. The operation and performance of the proposed contactless power converter are verified on a 7 W experimental circuit that provides an 18V/0.4A output from a 210-370 V input source.

• 전력전자학회논문지
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• 제7권2호
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• pp.121-128
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• 2002

새로운 에너지 회수 방식을 채용한 고효율 PDP 구동회로가 제안된다. 제안된 에너지 회수 회로는 PDP의 등가캐패시터에 저장된 에너지를 회수하기 위해서 종래의 에너지 회수 회로에서 부가되었던 별도의 보조 회로 없이 2개의 인덕터 만을 사용하므로 그 구조가 매우 간단하고 시스템 부피가 작으며 적은 수의 전력 소자만으로도 구현이 가능하므로 제작단가 절감효과를 얻을 수 있으며 높은 효율 등의 장점을 가지고 있다. 뿐만 아니라 PDP 화면에서 방사되는 광의 파형이 균일하고 안정적이므로 고화질을 보장하기도 한다. 제안된 회로의 유효성 검증을 위해 전 구간회로를 모두 갖춘 42인치 PDP를 스위칭 주파수 200kHz로 구동한 실험 결과를 제시하며, 본 논문에서 제안된 회로는 차세대 벽걸이형 컬러 TV에 매우 적합하게 적용될 수 있다.

• 전기전자학회논문지
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• 제25권1호
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• pp.206-211
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• 2021

본 논문에서는 열전에너지 하베스팅을 위한 자가 리셋(self-reset) 기능을 갖는 영점 전류 스위칭(Zero-Current Switching) 회로를 제안한다. 본 논문에서 제안하는 영점 전류 스위칭 회로는 전압비교기 회로에 자가 리셋 기능을 추가하여 전압비교기의 동작전류를 최소화함으로써 에너지 하베스팅 회로의 전력 소비를 줄이고 에너지 변환 효율을 향상시킬 수 있게 한다. 회로 시뮬레이션으로 본 논문에서 제안하는 영전 전류 스위칭 회로의 동작을 검증하고 성능을 평가한 결과, 열전에너지 하베스팅 회로의 출력전압-입력전압 비가 5.5 일 때, 기존의 영점 전류 스위칭 회로를 이용한 하베스팅 회로와의 비교를 통해서 본 논문의 하베스팅 회로의 전력효율이 3.4% 개선되는 것으로 평가된다. 본 논문에서 제안하는 영점 전류 스위칭 회로는 열전에너지 하베스팅의 응용 중에서 특히 저전력과 고에너지 효율 특성이 중요한 웨어러블, 바이오 헬스 관련된 하베스팅 회로의 성능 개선에 기여할 수 있을 것으로 생각된다.

• 센서학회지
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• 제33권3호
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• 진공이야기
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• 제2권2호
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• pp.12-16
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• 2015

Organic photovoltaics (OPVs) have attracted significant interest in an interdisciplinary research field for the decades as a next-generation photovoltaic device due to their unique advantages. One of requirements for OPVs having high power conversion efficiency is the favorable energy level alignment between the electrode/organic and organic/organic interfaces to manage the exciton dissociation and improve the charge transport. In this review, strategies to enhance the OPV performance by controlling the energy level alignment are discussed. The insertion of an exciton blocking layer leads to the efficient dissociation of photogenerated excitons at the donor/acceptor interface enhancing the short-circuit current density. The choice of a donor having a high ionization energy and an acceptor having a low electron affinity increases the open-circuit voltage. The insertion of an appropriate work function modifier which reduces the charge injection barrier removes the S-kink in current density-voltage characteristics of OPVs and improves the fill factor. This review would give a valuable guide to design the efficient OPV structure.