• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• ETRI Journal
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• v.44 no.3
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• pp.491-503
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• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.351-356
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• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• Journal of Information Display
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• v.2 no.4
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• pp.63-67
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• 2001

The switching power loss due to the panel capacitance during sustain period in AC PDP driving system can be minimized by using the energy recovery circuits. We proposed a new energy recovery circuit, SER1 (Seoul national univ. Energy Recovery circuit 1st). The experimental results of its application to a 42-inch surface discharge type AC PDP showed superior performance of SER1 in energy recovery efficiency and low distortion voltage waveform. Energy recovery efficiency of SER1 was measured up to 92.3 %, and the power dissipation during the sustain period was reduced by 15.2 W in 2000 pulse/frame compared with serial LC resonance energy recovery circuit.

• Journal of Power Electronics
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• v.7 no.4
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• pp.294-300
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• 2007

This paper deals with a design of a bootstrap power supply using snubber energy regeneration, which is used to power a high-side gate driver of a half-bridge circuit. In the proposed circuit, the energy stored in the low-side snubber capacitor is transferred to the high-side bootstrap capacitor without any magnetic components. Thus, the power dissipation in the RCD snubber can be effectively reduced. The operation principle and design method of the proposed circuit are presented. The experimental results are also provided to show the validity of the proposed circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.760-767
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• 2014

This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65nm CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-MHz frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of $0.73-fJ/cycle{\cdot}ns{\cdot}{\lambda}^2$.

• The Journal of the Convergence on Culture Technology
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• v.6 no.2
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• pp.521-527
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• 2020

Quantum-dot cellular automata (QCA) is a technology that attracts attention as a next-generation digital circuit design technology, and several digital circuits have been proposed in the QCA environment. Content-addressable memory (CAM) is a storage device that conducts a search based on information stored therein and provides fast speed in a special process such as network switching. Existing CAM cell circuits proposed in the QCA environment have a disadvantage in that a required area and energy dissipation are large. The CAM cell is composed of a memory unit that stores information and a match unit that determines whether or not the search is successful, and this study proposes an improved QCA CAM cell by designing the memory unit in a multi-layer structure. The proposed circuit uses simulation to verify the operation and compares and analyzes with the existing circuit.

• The Journal of the Acoustical Society of Korea
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• v.21 no.2
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• pp.150-159
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• 2002

The possibility of a broadband noise reduction of piezoelectric smart panels is experimentally studied. Piezoelectric smart panel is basically a plate structure on which piezoelectric patch with shunt circuits is mounted and sound absorbing material is bonded on the surface of the structure. Sound absorbing materials can absorb the sound transmitted at mid frequency region effectively while the use of piezoelectric shunt damping can reduce the transmission at resonance frequencies of the panel structure. To be able to tune the piezoelectric shunt circuit, the measured electrical impedance model is adopted. Resonant shunt circuit composed of register and inductor in stories is considered and the circuit parameters are determined based on maximizing the dissipated energy through the circuit. The transmitted noise reduction performance of smart panels is investigated using an acoustic tunnel. The tunnel is a square crosses sectional tunnel and a loud speaker is mounted at one side of the tunnel as a sound source. Panels are mounted in the middle of the tunnel and the transmitted sound pressure across the panels is measured. Noise reduction performance of a double smart panel possessing absorbing material and air gap shows a good result at mid frequency region except the first resonance frequency. By enabling the piezoelectric shunt damping, noise reduction is achieved at the resonance frequency as well. Piezoelectric smart panels incorporating passive method and piezoelectric shunt damping are a promising technology for noise reduction in a broadband frequency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.3 no.1
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• pp.49-57
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• 2002

The possibility of a transmission noise reduction of piezoelectric smart panels using piezoelectric shunt damping is experimentally studied. Piezoelectric smart panel is basically a plate structure on which piezoelectric patch with shunt circuits is mounted and sound absorbing materials are bonded on the surface of the structure. Sound absorbing materials can absorb the sound transmitted at mid frequency region effectively while the use of piezoelectric shunt damping can reduce the transmission at resonance frequencies of the panel structure. To be able to reduce the sound transmission at low panel resonances, piezoelectric damping using the measured electrical impedance model is adopted. Resonant shunt circuit for piezoelectric shunt damping is composed of register and inductor in series, and they are determined by maximizing the dissipated energy throughout the circuit. The transmitted noise reduction performance of smart panels is investigated using an acoustic tunnel. The tunnel is a tube with square crosses section and a loud-speaker is mounted at one side of the tube as a sound source. Panels are mounted in the middle of the tunnel and the transmitted sound pressure across panels is measured. Noise reduction performance of a smart panels possessing absorbing material and/or air gap shows a good result at mid frequency region but little effect in the resonance frequency. By enabling the piezoelectric shunt damping, noise reduction of 10dB, 8dB is achieved at the resonance frequencise as well. Piezoelectric smart panels incorporating passive method and piezoelectric shunt damping are a promising technology for noise reduction in a broadband frequency.