• IEMEK Journal of Embedded Systems and Applications
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• v.5 no.4
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• pp.217-224
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• 2010

Nowadays, people perform their tasks anywhere anytime using their mobile devices. For this reason, data synchronization (DS) between mobile devices and a central server has become one of the most essential technologies in mobile environments. Currently, several mobile DS protocols are proposed and used. However, the existing DS protocols cannot guarantee interoperability between them. To solve the problem, an embedded DS gateway has been developed in our previous study. The gateway runs on a Windows Mobile-based emulator. It converts data on a mobile device into common data specified by OMA DS standard protocol and vice versa. The embedded gateway has been built to support the OMA DS standard protocol. In order to verify that the embedded gateway conforms to the OMA DS standard protocol, two kinds of OMA conformance tests have to be conducted - interoperability test with an OMA DS-based server and conformance test with SCTS (SyncML Conformance Test Suit). In this paper, some parts of the gateway previously built are modified and the modified gateway is installed on a Windows Mobile-based smart phone. And the interoperability test and the conformance test with the SCTS are conducted. The results of the tests show that the embedded DS gateway operates properly on the Windows Mobile-based smart phone and that the gateway passes the tests, verifying its conformity to the OMA DS standard protocol. In addition, DS performance tests show that DS delay times between a real smart phone and a DS server increase gently as the number of DS data increases. In other words, the embedded DS gateway built in this paper can be used for a real smart phone at a reasonable performance cost.

• Journal of the Korea Society of Computer and Information
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• v.14 no.1
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• pp.17-24
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• 2009

According to increasing requirments in embedded systems, embedded software has been more complicated then before, a software developer is required to test her/his software to make a efficient embedded system software in both time and space. This paper suggests a testing tool with which a software developer can easily test the embedded system software in cross-development environments. The suggested tool is designed based on host/target architecture, to provide an intuitive test environment in which a test case can be executed in a target board. The tool uses an XML-based test script to generate an appropriate test case. It includes a tree-based test script editor with which a developer can easily make a test case. Therefore, with the suggested tool, a develop can put down a burden on an software testing and get more productivity in software development related on embedded system.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.05a
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• pp.603-606
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• 2004

Automatic test case generation for testing an embedded software is considered. Existing tools for test case generation such as finite state machine or mutant test usually adopt top down approach and depend upon graphical transition and decision table, which makes it difficult to find out where the bugs exist. Also it is hard to describe the special features of embedded systems such as concurrent execution of individual components. Most of embedded systems interacts with the real world, receiving signals through sensors or switches and sending output signals to actuators that somehow manipulate the environment. Embedded software controls the entire system based on the logics such as interpreting the sensor inputs and making the actuators to start or stop their intended operation. This study proposes an automatic test case generation procedure that tests the system starting from the control logics of sensors, switches and actuators and then their concurrent execution controls, and finally the entire system operation. Such a stepwise approach makes it easy to generate test cases to tell where the bugs of embedded software exist.

• 한국IT서비스학회:학술대회논문집
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• 2003.11a
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• pp.713-721
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• 2003

The time to market and productivity of embedded system needs a quality measurement process management of embedded software. But, defect management without preemptive analysis or prediction is not useful for quality measurement process management. This subject is focused on the defect that is one of the most important attributes of software measure in the process. Defining of defect attribute and quality measurement process management is according to understanding of embedded sw characteristics and defect data. So, this study contributes to propose the good method of the quantitative based on defect management in the test phase of sw lifecycle.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.22-34
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• 1999

In this paper, an efficient test algorithm for embedded dual-port memories is presented. The proposed test algorithm can be used to test embedded dual-port memories faster than the conventional multi-port test algorithms and can be used to completely detect stuck-at faults, transition faults and coupling faults which are major target faults in embedded memories. Also, in this work, BIST which performs the proposed memory testing algorithm is designed using Verilog-HDL, and simulation and synthesis for BIST are performed using Cadence Verilog-XL and Synopsys Design-Analyzer. It has been shown that the proposed test algorithm has high efficiency through experiments on various size of embedded memories.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1E
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• pp.14-19
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• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.56-61
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• 2013

Modern integrated circuits (ICs) are becoming an integrated parts of analog, digital, and radio frequency (RF) circuits. Testing these RF circuits on a chip is an important task, not only for fabrication quality control but also for tuning RF circuit elements to fit multi-standard wireless systems. In this paper, RF test circuits suitable for embedded testing are introduced: RF power detectors, power control circuits, directional couplers, and six-port reflectometers. Various types of embedded RF power detectors are reviewed. The conventional approach and our approach for the RF power control circuits are compared. Also, embedded tunable active directional couplers are presented. Then, six-port reflectometers for embedded RF testing are introduced including a 77-GHz six-port reflectometer circuit in a 130 nm process. This circuit demonstrates successful calibrated reflection coefficient simulation results for 37 well distributed samples in a Smith chart. The details including the theory, calibration, circuit design techniques, and simulations of the 77-GHz six-port reflectometer are presented in this paper.

• Proceedings of the KSR Conference
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• 2001.05a
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• pp.347-358
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• 2001

In this paper, we apply NHPP model example to s/w process in order to get to know s/w reliability. The test is constructed by a test zig of commercial product loaded real embedded system s/w. It is established to s/w reliability prediction and estimation of real-time embedded system s/w. It is computed the prediction value of cumulative failures, the failure intensity, the reliability and the estimation value of MTTF, Failure Rate. To the more realization of high reliability in the real-time embedded system s/w, if the embedded system s/w is ensured to the test coverage and constructed to stable s/w process ＆ operating system, we can improve the performance and the reliability characteristic of the real-time embedded system s/w.

• Journal of Korea Multimedia Society
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• v.4 no.6
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• pp.570-578
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• 2001

Boundary scan architecture test methodology was introduced to facilitate the testing of complex printed circuit board. The boundary scan architecture has a tremendous potential for real time monitoring of the operational status of a system without interference of normal system operation. In this paper, a new type of embedded controller for real time monitoring of the operational status of a system is proposed and designed by using boundary scan architecture. The proposed real time monitoring embedded controller consists of test access port controller and an embedded controller proposed real time monitoring embedded controller using boundary scan architecture can save the hard-wire resource and can easily interface with boundary scan architecture chip. Experimental results show that the real time monitoring using proposed embedded controller is more effective then the real time monitoring using host computer.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2004.05a
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• pp.607-610
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• 2004

It is still not sufficient for the famous embedded software test methods such as Finite State Machine, Software Cost Reduction and model coverage based test case generation, to pinpoint where bugs hang around and to figure out what makes the bugs. A new approach to ameliorate the drawbacks is proposed in this paper. In the approach, we define a generic model for embedded software. And we also define failure mechanism for embedded software, and a way to generate test cases based on it.