• Title/Summary/Keyword: Embedded Memory

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Data Transmission System from Distant Area Using SD-Card and Ethernet (SD 카드와 이더넷을 이용한 원격지 데이터 전송시스템)

  • Jo, Heung-Kuk
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.10a
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    • pp.381-385
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    • 2010
  • An aging Society solitary life old mans are increasing. The nurses have to visit old mans and must confirm their disease, because they do not act well. It is very difficult to take care old man, because the number of Nurses are small. This problem is solved by collection of data about condition of old mans from long distance. Data communication with Ethernet have benefit to collection of measurement of old man's condition. The Data storage system an long distance place are storaged data and after several day data was transmitted to the DB over the Ethernet. For Miniaturization of such system the system must be OS-less Embedded Ethernet Server system. Such system manages the file management system only with H/W. The Storage device is used SD-card. SD Card is small size and operates with small power. By using 512MB sd memory card, it is possible to storage during 5~6 years, 10 byte of temperature value per second. In this paper, we make a Embedded Ethernet Server using W3100A, Atmega128 MCU and data stroage device using SD-Card. This system operates with O/S-less Embedded Ethernet Server. We talk about file System, Storage and Ethernet. We explained about MCU Atmega128, Interface between LAN LSIand W3100A, Interface between W3100A and Phyceiver RTL8201, data I/O between MCU and SD-Card and File System. We shows the experiment device and result of monitoring.

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Garbage Collection Method using Proxy Block considering Index Data Structure based on Flash Memory (플래시 메모리 기반 인덱스 구조에서 대리블록 이용한 가비지 컬렉션 기법)

  • Kim, Seon Hwan;Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.6
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    • pp.1-11
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    • 2015
  • Recently, NAND flash memories are used for storage devices because of fast access speed and low-power. However, applications of FTL on low power computing devices lead to heavy workloads which result in a memory requirement and an implementation overhead. Consequently, studies of B+-Tree on embedded devices without the FTL have been proposed. The studies of B+-Tree are optimized for performance of inserting and updating records, considering to disadvantages of the NAND flash memory that it can not support in-place update. However, if a general garbage collection method is applied to the previous studies of B+-Tree, a performance of the B+-Tree is reduced, because it generates a rearrangement of the B+-Tree by changing of page positions on the NAND flash memory. Therefor, we propose a novel garbage collection method which can apply to the B+-Tree based on the NAND flash memory without the FTL. The proposed garbage collection method does not generate a rearrangement of the B+-Tree by using a block information table and a proxy block. We implemented the B+-Tree and ${\mu}$-Tree with the proposed garbage collection on physical devices with the NAND flash memory. In experiment results, the proposed garbage collection scheme compared to greedy algorithm garbage collection scheme increased the number of inserted keys by up to about 73% on B+-Tree and decreased elapsed time of garbage collection by up to about 39% on ${\mu}$-Tree.

An In-Depth Analysis and Improvement on Cache Mechanisms of SSD FTL (SSD FTL의 캐시 메커니즘에 대한 심층 분석 및 개선)

  • Lee, Hyung-Bong;Chung, Tae-Yun
    • IEMEK Journal of Embedded Systems and Applications
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    • v.15 no.1
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    • pp.9-16
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    • 2020
  • Recently, the capacity of SSD has been increasing rapidly due to the improvement of flash memory density. To take full advantage of these SSDs, first of all, FTL's prompt adaptation is necessary. The FTL is a translation layer existing in SSDs to overcome the drawback of the SSD that cannot be modified in place, and has garbage collection and caching functions in addition to the map table management function. In this study, we focus on caching function, compare and analyze the cache implementation methodologies, and propose improved methods. Typical cache implementations divide the cache into groups, manage and retrieve the caches in the group as a linked list. Thus, searches are made in the order of the linked list. In contrast, we propose a method of sequential searching using the search area group of a cache registered in the map table regardless of the linked list and cache group. Experimental results show that the proposed method has a 2.5 times improvement over the conventional method.

Design of Traffic Metering System using Embedded Linux (임베디드 리눅스를 이용한 트래픽 미터링 시스템 설계)

  • Lee, Heung-Jae;Jeon, Hee-Jin;Choe, Jin-Kyu;Lee, Kyou-Ho
    • Journal of IKEEE
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    • v.9 no.2 s.17
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    • pp.79-86
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    • 2005
  • Increasing network traffic and multimedia application services need realtime analysis of network traffic for improvement of QoS and effective management of network resource. Because difficulty of measurement based on software method, study of meter architecture for efficient capture function is necessary. Therefore we design and implement hardware metering system for efficient packet capture using embedded linux. And we analyze required bandwidth of system bus and memory for 10Gbps traffic through simulation.

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An Advanced Embedded SRAM Cell with Expanded Read/Write Stability and Leakage Reduction

  • Chung, Yeon-Bae
    • Journal of IKEEE
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    • v.16 no.3
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    • pp.265-273
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    • 2012
  • Data stability and leakage power dissipation have become a critical issue in scaled SRAM design. In this paper, an advanced 8T SRAM cell improving the read and write stability of data storage elements as well as reducing the leakage current in the idle mode is presented. During the read operation, the bit-cell keeps the noise-vulnerable data 'low' node voltage close to the ground level, and thus producing near-ideal voltage transfer characteristics essential for robust read functionality. In the write operation, a negative bias on the cell facilitates to change the contents of the bit. Unlike the conventional 6T cell, there is no conflicting read and write requirement on sizing the transistors. In the standby mode, the built-in stacked device in the 8T cell reduces the leakage current significantly. The 8T SRAM cell implemented in a 130 nm CMOS technology demonstrates almost 100 % higher read stability while bearing 20 % better write-ability at 1.2 V typical condition, and a reduction by 45 % in leakage power consumption compared to the standard 6T cell. The stability enhancement and leakage power reduction provided with the proposed bit-cell are confirmed under process, voltage and temperature variations.

Implementation of an Automatic Sunrise Household Lighting System Using a PIC Microcontroller (PIC 마이크로컨트롤러를 이용한 가정용 자동해돋이 조명시스템 구현)

  • Kang Brian B.;Kang Chul-Goo
    • Journal of the Korean Society for Precision Engineering
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    • v.22 no.12 s.177
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    • pp.70-76
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    • 2005
  • It is known that natural awakening of us in the morning is due to stimulation of the reticular activation system through biological clock in the suprachiasmatic nucleus of hypothalamus by the morning sunlight. If we sleep at dark rooms without windows and so without morning sunlight, thus, it is not easy fur us to get up refreshingly in the morning. In this paper, we propose an automatic sunrise household lighting system that helps us fer getting up cheerfully in the morning even if we sleep in dark rooms without morning sunlight. The proposed lighting system is an embedded system that turns automatically on the electric lamp and makes it brighter and brighter coincidently with the actual sunrise. The proposed system is composed of a PIC microcontroller with flash memory, a real-time clock IC, a D/A converter, an amplifier, a dimmer unit, a light bulb, a display panel and a keyboard. The validity of the proposed intelligent lighting system is demonstrated via a prototype production and experimentation.

Development of WLAN AP based on IBM 405GP (IBM PowerPC 405GP를 이용한 Wireless LAN Access Point 개발에 관한 연구)

  • Kim Do-Gyu
    • The Journal of Information Technology
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    • v.6 no.3
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    • pp.65-73
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    • 2003
  • The evaluation AP embedded Linux board is implemented. The board is made of IBM 405 GP processor, PPCBoot-1.2.1 boot loader, Linux-2.4.21 kernel and root file system. The evaluation board has two flash memories, boot flash and application flash of size 512Kbyte and 16Mbyte, respectively. And it supports IEEE 802.11a which provide the maximum throughput of 54Mbps in the 5.2GHz frequency band. MTD(Memory Technology Device) and JFFS2(Journalling Flash File System version 2) technologies are adopted to optimally package the system software, boot loader, kernel and root file system. And in order to optimize root file system, busybox package and tiny login are used. Linux kernel and root file system is combined together with mkimage utility.

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Embedded File System for Ubiquitous Computing (유비쿼터스 컴퓨팅을 위한 임베디드 파일시스템)

  • Lee, Byung-Kwon;Ju, Young-Kwan;Kim, Suk-Il;Jeon, Joong-Nam
    • Journal of the Korean Institute of Intelligent Systems
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    • v.14 no.4
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    • pp.424-430
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    • 2004
  • This paper explains the construction of the filesystems which could be utilized in embedded systems as an implementation of ubiquitous computing. It includes the formal architecture of filesystem hierarchy for the DOC (Disk-On-Chip) filesystem and the flash filesystem based on the MTD (Memory Technology Devices). For DOC, the root filesystem and the user filesystem are constructed by the TrueFFS supported by the M-Systems. For MTD filesystem, the root filesystem is implemented in the fast RAM disk, and the user filesystem is implemented in the JFFS2 that supports large capacity. In order to support the GUI filesystem, the porting process of Qt/E is also included in this paper.

Analysis of I/O Response Time Throughout NVMe Driver Implementation Architectures (NVMe 드라이버 구현 방식에 따른 I/O 응답시간 분석)

  • Kang, Ingu;Joo, Yongsoo;Lim, Sung-Soo
    • IEMEK Journal of Embedded Systems and Applications
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    • v.12 no.3
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    • pp.139-147
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    • 2017
  • In recent years, non-volatile memory express (NVMe), a new host controller interface standard, has been adapted to overcome performance bottlenecks caused by the acceleration of solid state drives (SSD). Recently, performance breakthrough cases over AHCI based SATA SSDs by adapting NVMe based PCI Express (PCIe) SSD to servers and PCs have been reported. Furthermore, replacing legacy eMMC-flash storage with NVMe based storage is also considered for next generation of mobile devices such as smartphones. The Linux kernel includes drivers for NVMe support, and as the kernel version increases, the implementation of the NVMe driver code has changed. However, mobile devices are often equipped with older versions of Android operating systems (OSes), where the newest features of NVMe drivers are not available. Therefore, different features of different NVMe driver implementations are not well evaluated on Android OSes. In this paper, we analyze the response time of the NVMe driver for various Linux kernel version.

Separate Signature Monitoring for Control Flow Error Detection (제어흐름 에러 탐지를 위한 분리형 시그니처 모니터링 기법)

  • Choi, Kiho;Park, Daejin;Cho, Jeonghun
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.5
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    • pp.225-234
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    • 2018
  • Control flow errors are caused by the vulnerability of memory and result in system failure. Signature-based control flow monitoring is a representative method for alleviating the problem. The method commonly consists of two routines; one routine is signature update and the other is signature verification. However, in the existing signature-based control flow monitoring, monitoring target application is tightly combined with the monitoring code, and the operation of monitoring in a single thread is the basic model. This makes the signature-based monitoring method difficult to expect performance improvement that can be taken in multi-thread and multi-core environments. In this paper, we propose a new signature-based control flow monitoring model that separates signature update and signature verification in thread level. The signature update is combined with application thread and signature verification runs on a separate monitor thread. In the proposed model, the application thread and the monitor thread are separated from each other, so that we can expect a performance improvement that can be taken in a multi-core and multi-thread environment.