• Journal of Sensor Science and Technology
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• v.25 no.6
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• pp.440-446
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• 2016

This study introduces the characteristics of current-voltage (I-V) and impedance variance for $ZnO-Zn_2BiVO_6-Co_3O_4$ (ZZCo), which is sintered at $900^{\circ}C$, according to temperature changes. ZZCo varistor demonstrates dramatic improvement of non-linear coefficient, ${\alpha}=66$, with lower leakage current and higher insulating resistivity than those of ZZ ($ZnO-Zn_2BiVO_6$) from the aspect of I-V curves. While both systems are thermally stable up to $125^{\circ}C$, ZZCo represents a higher grain boundary activation energy with 1.05 eV and 0.94 eV of J-E-T and from IS & MS, respectively, than that of ZZ with 0.73 eV and 0.82 eV of J-E-T and from IS & MS, respectively, in the region above $180^{\circ}C$. It could be attributed to the formation of $V^*_o$(0.41~0.47 eV) as dominant defect in two systems, as well as the defect-induced capacitance increase from 781 pF to 1 nF in accordance with increasing temperature. On the other hand, both the grain boundary capacitances of ZZ and ZZCo are shown to decrease to 357 pF and 349 pF, respectively, while the resistances systems decreased exponentially, in accordance with increasing temperature. So, this paper suggests that the application of newly formed liquid phases as sintering additives in both $Zn_2BiVO_6$ and the ZZCo-based varistors would be helpful in developing commercialized devices such as chips, disk-type ZnO varistors in the future.

• Land and Housing Review
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• v.12 no.2
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• pp.121-139
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• 2021

Technical documents in the construction field are changing from paper documents to electronic ones. As a result, the industry witnesses a trend of using portable electronic devices in searching or retrieving necessary information such as relevant regulations. Despite the improvement in the accessibility to general technical documents, a limitation is still found in accessing the electronic documents on the regulations. We see the barrier for field engineers to enhance their technical knowledge. One of major barriers is that videos, animations, and virtual reality information to enhance the visual understanding of technical content related to regulations are not linked. It is the interactive electronic technical manual (IETM) that can address such issues. The IETM is an electronic document system that enables real-time information acquisition while operating in the form of conversations with users by linking multimedia functions to document types such as specifications and guidelines. This study establishes a model of the IETM that can be operated in the planning stage of a construction project. The study also verifies its usability with a hypothetical case study. This study aims to improve the usability of the IETM in the construction project by analyzing the application effect of the IETM using the AHP technique.

• Applied Chemistry for Engineering
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• v.34 no.4
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• pp.444-449
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• 2023

As electronic devices become smaller and more integrated, the demand for manufacturing thin, flexible printed circuit boards (FPCBs) has increased. Although FPCBs are conventionally manufactured by a photolithography method using dry film resist, this process is complicated, and the mask is specifically designed to obtain the precision of the desired circuit line width. In this regard, manufacturing FPCBs with fine patterns through the direct printing method of photocurable inks has gained growing attention. Since the manufacturing process of FPCBs is based on the direct printing method that includes etching and stripping processes utilizing acid and basic chemicals, controlling the adhesion strength, the etching resistance, and the strippability of photocured inks has drawn a lot of attention for the fabrication of fine patterns through photocurable inks. In this study, acrylic ink with various types and contents of the photoinitiator was prepared, and the curing behavior was analyzed. Also, the adhesion strength, etching resistance, and strippability were analyzed to evaluate the applicability of developed photocurable etching resist inks.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.664-667
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• 2011

In this paper, threshold voltage characteristics have been analyzed as one of short channel effects occurred in double gate(DG)MOSFET to be next-generation devices. The Gaussian function to be nearly experimental distribution has been used as carrier distribution to solve Poisson's equation, and threshold voltage has been investigated according to projected range and standard projected deviation, variables of Gaussian function. The analytical potential distribution model has been derived from Poisson's equation, and threshold voltage has been obtained from this model. Since threshold voltage has been defined as gate voltage when surface potential is twice of Fermi potential, threshold voltage has been derived from analytical model of surface potential. Those results of this potential model are compared with those of numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with numerical model, the threshold voltage characteristics have been considered according to the doping profile of DGMOSFET.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.155.2-155.2
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• 2013

Strain-relaxed SiGe layer on Si substrate has numerous potential applications for electronic and opto- electronic devices. SiGe layer must have a high degree of strain relaxation and a low dislocation density. Conventionally, strain-relaxed SiGe on Si has been manufactured using compositionally graded buffers, in which very thick SiGe buffers of several micrometers are grown on a Si substrate with Ge composition increasing from the Si substrate to the surface. In this study, a new plasma process, i.e., the combination of PIII&D and HiPIMS, was adopted to implant Ge ions into Si wafer for direct formation of SiGe layer on Si substrate. Due to the high peak power density applied the Ge sputtering target during HiPIMS operation, a large fraction of sputtered Ge atoms is ionized. If the negative high voltage pulse applied to the sample stage in PIII&D system is synchronized with the pulsed Ge plasma, the ion implantation of Ge ions can be successfully accomplished. The PIII&D system for Ge ion implantation on Si (100) substrate was equipped with 3'-magnetron sputtering guns with Ge and Si target, which were operated with a HiPIMS pulsed-DC power supply. The sample stage with Si substrate was pulse-biased using a separate hard-tube pulser. During the implantation operation, HiPIMS pulse and substrate's negative bias pulse were synchronized at the same frequency of 50 Hz. The pulse voltage applied to the Ge sputtering target was -1200 V and the pulse width was 80 usec. While operating the Ge sputtering gun in HiPIMS mode, a pulse bias of -50 kV was applied to the Si substrate. The pulse width was 50 usec with a 30 usec delay time with respect to the HiPIMS pulse. Ge ion implantation process was performed for 30 min. to achieve approximately 20 % of Ge concentration in Si substrate. Right after Ge ion implantation, ~50 nm thick Si capping layer was deposited to prevent oxidation during subsequent RTA process at $1000^{\circ}C$ in N2 environment. The Ge-implanted Si samples were analyzed using Auger electron spectroscopy, High-resolution X-ray diffractometer, Raman spectroscopy, and Transmission electron microscopy to investigate the depth distribution, the degree of strain relaxation, and the crystalline structure, respectively. The analysis results showed that a strain-relaxed SiGe layer of ~100 nm thickness could be effectively formed on Si substrate by direct Ge ion implantation using the newly-developed PIII&D process for non-gaseous elements.

• Journal of Broadcast Engineering
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• v.26 no.6
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• pp.680-691
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• 2021

Due to the recent developments of attaining 3D contents by using devices such as 3D scanners, the diversity of the contents being used in AR(Augmented Reality)/VR(Virutal Reality) fields is significantly increasing. There are several ways to represent 3D data, and using point clouds is one of them. A point cloud is a cluster of points, having the advantage of being able to attain actual 3D data with high precision. However, in order to express 3D contents, much more data is required compared to that of 2D images. The size of data needed to represent dynamic 3D point cloud objects that consists of multiple frames is especially big, and that is why an efficient compression technology for this kind of data must be developed. In this paper, a motion estimation and compensation method for dynamic point cloud objects using 3D DCT is proposed. This will lead to switching the 3D video frames into I frames and P frames, which ensures higher compression ratio. Then, we confirm the compression efficiency of the proposed technology by comparing it with the anchor technology, an Intra-frame based compression method, and 2D-DCT based V-PCC.

• Journal of Sensor Science and Technology
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• v.28 no.1
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• pp.41-46
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• 2019

In order to develop novel thermal imaging materials for microbolometer applications, $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ ($0.18{\leq}x{\leq}0.26$) thin films were fabricated using metal-organic decomposition. Effects of Cu content on the electrical properties of the annealed films were investigated. Spinel thin films with a thickness of approximately 100 nm were obtained from the $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ films annealed at $380^{\circ}C$ for five hours. The resistivity (${\rho}$) of the annealed films was analyzed with respect to the small polaron hopping model. Based on the $Mn^{3+}/Mn^{4+}$ ratio values obtained through x-ray photoelectron spectroscopy analysis, the hopping mechanism between $Mn^{3+}$ and $Mn^{4+}$ cations discussed in the proposed study. The effects of $Cu^+$ and $Cu^{2+}$ cations on the hopping mechanism is also discussed. Obtained results indicate that $[(Ni_{0.3}Mn_{0.7})_{1-x}Cu_x]_3O_4$ thin films with low temperature annealing and superior electrical properties (${\rho}{\leq}54.83{\Omega}{\cdot}cm$, temperature coefficient of resistance > -2.62%/K) can be effectively employed in applications involving complementary metal-oxide semiconductor (CMOS) integrated microbolometer devices.

• Journal of Electrical Engineering and Technology
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• v.1 no.2
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• pp.216-225
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• 2006

This paper presents a new circuit topology of DC busline switch and snubbing capacitor-assisted full-bridge soft-switching PWM inverter type DC-DC power converter with a high frequency link for low voltage large current applications as DC feeding systems, telecommunication power plants, automotive DC bus converters, plasma generator, electro plating plants, fuel cell interfaced power conditioner and arc welding power supplies. The proposed power converter circuit is based upon a voltage source-fed H type full-bridge high frequency PWM inverter with a high frequency transformer link. The conventional type high frequency inverter circuit is modified by adding a single power semiconductor switching device in series with DC rail and snubbing lossless capacitor in parallel with the inverter bridge legs. All the active power switches in the full-bridge inverter arms and DC busline can achieve ZVS/ZVT turn-off and ZCS turn-on commutation operation. Therefore, the total switching losses at turn-off and turn-on switching transitions of these power semiconductor devices can be reduced even in the high switching frequency bands ranging from 20 kHz to 100 kHz. The switching frequency of this DC-DC power converter using IGBT power modules is selected to be 60 kHz. It is proved experimentally by the power loss analysis that the more the switching frequency increases, the more the proposed DC-DC converter can achieve high performance, lighter in weight, lower power losses and miniaturization in size as compared to the conventional hard switching one. The principle of operation, operation modes, practical and inherent effectiveness of this novel DC-DC power converter topology is proved for a low voltage and large current DC-DC power supplies of arc welder applications in industry.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.101-109
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• 2016

The images captured by digital still cameras or mobile phones are not always satisfactory because the devices have limited dynamic ranges compared with that of the real world. To cope with the problems, tone mapping function based methods and retinex theory based methods are studied. However, these methods generate a halo artifact or limited enhancement of global and local contrasts. The proposed method estimates illumination information used for image enhancement by optimizing a dynamic range of input image. The estimated illumination information has smoothness characteristic where the luminance is flat and does not have where the luminance changes to prevent the halo artifact. Additionally, the estimated illumination information and surrounding pixel values are considered when the tone mapping function is applied to overcome the limitations of the conventional tone mapping function approach. Experimental results show that the proposed algorithm outperforms the conventional methods on objective and subjective criteria.