• Title/Summary/Keyword: Electronic devices

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Electrical characteristics of ZnO nanowire - CdTe nanoparticle nano floating gate memory device (ZnO 나노선과 CdTe 나노입자를 이용한 NFGM 소자의 전기적 특성)

  • Yoon, Chang-Joon;Yeom, Dong-Hyuk;Kang, Jeong-Min;Jeong, Dong-Young;Kim, Mi-Hyun;Koh, Eui-Kwan;Koo, Sang-Mo;Kim, Sang-Sig
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.136-137
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    • 2007
  • In this study, a single ZnO nanowire - CdTe nanoparticle nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of ZnO nanowire-based field effect transistor (FET) devices with CdTe nanoparticles embedded in the $Al_2O_3$ gate materials and without the CdTe nanoparticles.

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A Study of End Point Detection Measurement for STI-CMP Applications (STI-CMP 공정 적용을 위한 연마 정지점 고찰)

  • 이경태;김상용;김창일;서용진;장의구
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.90-93
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    • 2000
  • In this study, the rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STI CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. To resolve these problems, the development of slurry for CMP with high removal rate and high selectivity between each thin films was studied then it can be prevent the reasons of many defects by reasons of many defects by simplification of process that directly apply CMP process to STI structure without the reverse moat pattern process.

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A properties of ZnO thin film deposited by magnetron sputtering and its resistivity and microstructure due to annealing (Magnetron sputtering으로 증착한 ZnO 박막의 특성과 열처리에 따른 비저항과 미세구조)

  • 이승환;성영권;김종관
    • Electrical & Electronic Materials
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    • v.10 no.2
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    • pp.126-133
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    • 1997
  • In order to apply for the gas sensing layer and the piezoelectric thin film devices, we studied the effects of magnetron sputtering conditions and annealing temperature on the electrical and structual characteristics of the ZnO thin film. The optimal deposition conditions, in order to obtain a c axis of the ZnO (002) phase thin film which is perpendicular to SiO$_{2}$/Si substrate, were like these ; substrate temperature 150.deg. C, chamber pressure 2 mtorr, R.F. power 300 watts, gas flow ratio 0.4[O$_{2}$(Ar + $O_{2}$)]. When the ZnO thin film was annealed in 600.deg. C, $O_{2}$ gas ambient for 1 hr, the resistivity was 2.6 x 10$^{2}$.ohm.cm and the grain size of ZnO thin film was less than 1 .mu.m. So the ZnO thin film acquired from above conditions can apply for the gas sensing layer which require a c axis perpendicular to the substrate surface.

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SAXS and AFM Study on Porous Silicon Prepared by Anodic Etching in HF-based Solution (SAXS와 AFM에 의한 HF-용액내 양극 에칭에 의해 제조된 기공성 실리콘의 구조연구)

  • Kim, Eu-gene;Kim, Hwa-Joong
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.17 no.11
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    • pp.1218-1223
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    • 2004
  • Porous silicon materials have been shown to have bright prospects for applications in light emitting, solar cell, as well as light- and chemical-sensing devices. In this report, structures of porous silicon prepared by anodic etching in HF-based solution with various etching times were studied in detail by Atomic Force Microscopy and Small Angle X -ray Scattering technique using the high energy beam line at Pohang Light Source in Korea. The results showed the coexistence of the various pores with nanometer and submicrometer scales. For nanameter size pores, the mixed ones with two different shapes were identified: the larger ones in cylindrical shape and the smaller ones in spherical shape. Volume fractions of the cylindrical and the spherical pores were about equal and remained unchanged at all etching times investigated. On the whole uniform values of the specific surface area and of the size parameters of the pores were observed except for the larger specific surface area for the sample with the short etching time. The results implies that etching process causes the inner surfaces to become smoother while new pores are being generated. In all SAXS data at large Q vectors, Porod slope of -4 was observed, which supports the fact that the pores have smooth surfaces.

Reliability Evaluation Criteria and Multi-Stress Aging Test for Polymer Insulator (폴리머 현수애자의 신뢰성 평가 및 복합가속열화 방법)

  • Park, Hoy-Yul;Kang, Dong-Pil;Ahn, Myeong-Sang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.469-472
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    • 2004
  • There have been numerous accelerated aging laboratory tests for evaluating suitability of polymeric materials and devices. Aging test for materials and its full scale device has been conducted, but poor correlation of aging test such as service experience were observed. Service experience plays a key role in the utility section of composite insulators. A meaningful and reliable accelerated aging test is needed for evaluating composite insulator. During the service these insulators are subjected to aging stress such as humidity, pollution, and electrical field, and erosion and tracking of the weathershed occurs. This paper presents the criteria of reliability evaluation and evaluation facilities for 22.9 kV suspension composite insulator. We adopt the criteria of reliability evaluation consist of two test methods. One is CEA tracking wheel test for examining the tracking and erosion performance of composite insulator. The other is multi-stress aging test for examining effects of environmental factors such as UV, temperature, humidity, etc on composite insulator.

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Effect of substrate bias on electrical properties of ZnO:Al transparent conducting film (ZnO:Al투명전도막의 전기적 특성에 미치는 Bias 전압의 영향)

  • Park, Kang-Il;Kim, Byung-Sub;Lim, Dong-Gun;Lee, Su-Ho;Kwak, Dong-Joo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.408-411
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    • 2003
  • Al doped Zinc Oxide(ZnO:Al) films, which is widely used as a transparent conductor in optoelectronic devices such as solar cell, liquid crystal display, plasma display panel, thermal heater, and other sensors, were prepared by using the capacitively coupled DC magnetron sputtering method. The influence of the substrate temperature, working gas pressure, discharge power and doping amounts of Al on the electrical, optical and morphological properties were investigated experimentally. The effect of bias voltage on the electrical properties of ZnO thin film were also studied. Films with lowest resistivity of $5.4{\times}10^{-4}\;{\Omega}-cm$ have been achieved in case of films deposited at 1mtorr, $400^{\circ}C$ with a substrate bias of +10V for 840nm in film thickness.

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Characteristics of OLEDs Using $Alq_2-Ncd\;and\;Alq_2-Nq$ as Emitting Layer ($Alq_2-Ncd$$Alq_2-Nq$를 이용한 유기전기발광 소자의 특성)

  • Yang, Ki-Sung;Shin, Hoon-Kyu;Kim, Chung-Kyun;Kwon, Young-Soo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.11a
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    • pp.447-450
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    • 2003
  • In this paper, new luminescent material, 6,11-dihydoxy-5,12-naphtacene-dione Alq3 complex (Alq2-Ncd), 1,4-dihydoxy-5,8-naphtaquinone Alq3 complex(Alq2-Nq) was synthesized. And extended efforts had been made to obtain high-performance electroluminescent(EL) devices, since the first report of organic light-emitting diodes(OLEDS) based on tris-(8-hydroxyquinoline) aluminum(Alq3). We have performed investigate characterization of the materials. Current-voltage characteristics, luminance-voltage characteristics and luminous efficiency were measured by Flat Panel Display Analysis System(Model 200-AT) at room temperature. An intensive research is going on to improve the device efficiency using the hole injection layer, different electrodes, and etc. By using the hole injection layer, the charge-injection can be controlled and the stability could be improved. This study indicates not only the sterical effect but also some other effects would be responsible for the change of the emission wavelength.

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Issues in CMP Technology and Future Challenges for Sub-100nm Devices (100nm 이하 Device에서의 CMP 기술의 문제점 및 향후 도전과제)

  • Yun, Seong-Kyu;Lee, Jae-Dong;Hong, Chang-Ki;Cho, Han-Ku;Moon, Joo-Tae;Ryu, Byoung-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.224-226
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    • 2004
  • CMP process requirements become tighter especially in sub-100nm technology. Especially, high planarity and low defectivity appear as leading issues in CMP technology. Also, the introduction of new materials and advanced lithography technique increases CMP applications. Here are listed some major issues and challenges in CMP technology, which can be categorized following four items. These have practical significance and should be considered more concretely for future generation.

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Reverse voltage characteristics of 4H SiC Schottky Diode by Edge termination Method (4H 탄화규소 쇼트키 다이오드에서 접합종단기법에 따른 항복전압특성)

  • Cheong, Hui-Jong;Bahng, Wook;Kang, In-Ho;Kim, Sang-Cheol;Han, Hyeon-Sook;Kim, Nam-Kyun;Lee, Yong-Jae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.191-192
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    • 2005
  • The reverse breakdown voltages of 4H-SiC SBD(schottky barrier diode)s with FP(Field Plate) and/or FLR(Field Limiting Ring) as a edge termination, were investigated. The breakdown voltages of SBDs with FP ware investigated varying the overlap width from $1{\mu}m$ to $30{\mu}m$. The maximum average breakdown voltages was 475V. There is no significant changes for the devices with overlap width of between $5{\mu}m\sim30{\mu}m$. It was confirmed that the dielectric breakdown of the thin thermal oxide is main cause of device failure. However, the breakdown voltage of SBD with FLR was 1400V even though the FLR edge termination structure was not optimized.

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The Effects of Deposition Rate on the Physical Characteristics of OLEDs (유기발광 다이오드의 물성에 미치는 증착속도의 영향)

  • Lee, Young-Hwan;Cha, Ki-Ho;Kim, Weon-Jong;Lee, Jong-Yong;Kim, Gwi-Yeol;Hong, Jin-Woong
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.04a
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    • pp.54-55
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    • 2006
  • Organic light-emitting diodes(OLEOs) are attractive because of possible application in display with low operating voltage, low power consumption, self-emission and capability of multicolor emission by the selection of emissive material. We investigated the effects of deposition rate on the electrical characteristics, physical characteristics and optical characteristics of OLEOs in the ITO(indium-tin-oxide)/N.N'-diphenyl-N,N'-bis(3-methyphenyl)-1,1'-biphenyl-4,4'-diamine(TPD)/tris(8-hydroxyquinoline)aluminum($Alq_3$)/Al device. We measured current density, luminous flux and luminance characteristics of devices with varying deposition rates of TPD and $Alq_3$. It has been found that optimal deposition rate of TPD and $Alq_3$ were respectively $1.5{\AA}/s$ from the device structure. An AFM measurement results, surface roughness of the deposited film was the lowest when deposition rate was $1.5{\AA}/s$.

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