• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.138-143
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• 2004

CMP (Chemical Mechanical Polishing) technology for global planarization of multilevel interconnection structure has been widely studied for the next generation devices. Among the consumables for CMP process, especially, slurry and their chemical compositions play a very important role in the removal rates and within-wafer non-uniformity (WIWNU) for global planarization ability of CMP process. However, CMP slurries contain abrasive particles exceeding 1 ${\mu}{\textrm}{m}$ size, which can cause micro-scratch on the wafer surface after CMP process. Such a large size particle in these slurries may be caused by particle agglomeration in slurry supply-line. In this work, to investigate the effects of agglomeration on the performance of oxide CMP slurry, we have studied an aging effect of silica slurry as a function of particle size distribution and aging time during one month. We Prepared and compared the self-developed silica slurry by adding of alumina powders. Also, we have investigated the oxide CMP characteristics. As an experimental result, we could be obtained the relatively stable slurry characteristics comparable to aging effect of original silica slurry. Consequently, we can expect the saving of high-cost slurry.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.4
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• pp.322-329
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• 2003

We have studied how surface pretilt angle affects generation of disclination line in liquid-crystal-on silicon cells for 45$^{\circ}$-twisted nematic (TN) and vertical alignment (VA) modes with pixel size of 15$\mu\textrm{m}$. Our studies show that when the pretilt angle is increased from 0$^{\circ}$to 3$^{\circ}$ in the 45$^{\circ}$-TN cell, the disclination line at left side of on-pixel becomes weak and is well suppressed with $\theta$$\_$p/=3$^{\circ}$ although the pixel size Is decreased. In the VA cell, when the pretilt angle is decreased from 89$^{\circ}$ to 86$^{\circ}$, the disclination line at right side of the on-pixel is suppressed well and even for a smaller pixel size, it does not exist when $\theta$$\_$p/=86$^{\circ}$. The results inform that the pretilt angle strongly affects the image quality of microdisplays.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.5
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• pp.432-436
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• 2006

The $ZnGa_2O_4$ and Mn, Cr-doped $ZnGa_2O_4$ Phosphors were synthesized through conventional solid state reactions. The XRD patterns show that the $ZnGa_2O_4$ has a (3 1 1) main peak and a spinel phase. The emission wavelength of $ZnGa_2O_4$ showed main peak of 420 nm and maximum intensity at the sintering temperature of $1100^{\circ}C$. In the crystalline $ZnGa_2O_4$, the Mn shows green emission (510 nm, $^4T_1-^6A_1$) with a quenching concentration of 0.6 mol%, and the Cr shows red emission (705 nm, $^4T_2-^4A_2$) with a quenching concentration of 2 mol%. These results indicate that $ZnGa_2O_4$ Phosphors hold promise for potential applications in field emission display devices with high brightness operating in full color regions.

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.208-211
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• 2009

The authors have demonstrated the various characteristics of hybrid white organic light-emitting diodes (HWOLED) using fluorescent blue and phosphorescent red emitters. We also demonstrated that two devices showed different characteristics in accordance with thickness of the 4,4′-N,N′-dicarbazole-biphenyl (CBP) spacer (CS) inserted between the blue and the red emitting layer. It was found that the device with a CS thickness of 70 $\AA$ showed a current efficiency 2.5 times higher than that of the control device with a CS thickness of 30 $\AA$ by preventing the triplet Dexter energy transfer from the red to the blue emitting layer. The HWOLED with the CS thickness of 70 $\AA$ exhibited a maximum luminance of 24500 cd/$m^2$, a maximum current efficiency of 42.9 cd/A, a power efficiency of 37.5 lm/W, and Commission Internationale de I'Eclairage coordinates of (0.37, 0.42).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1022-1026
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• 2007

We have demonstrated new functionalities of Ag doped chalcogenide glasses based on their capabilities as solid electrolytes. Formation of such amorphous systems by the introduction of silver via photo-induced diffusion in thin chalcogenide films is considered. The influence of silver on the properties of the newly formed materials is regarded in terms of diffusion kinetics and Ag saturation is related to the composition of the hosting material. Silver saturated chalcogenide glasses have been used in the formation of solid electrolyte which is the active medium in programmable metallization cell (PMC) devices. In this paper, we investigated electrical and optical properties of Ag-doped chalcogenide thin film on changed thickness of Ag and chalcogenide thin films, which is concerned at Ag-doping effect of PMC cell. As a result, when thickness of Ag and chalcogenide thin film was 30 nm and 50 nm respectively, device have excellent characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1056-1061
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• 2007

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. In this study, we aimed to systematically investigate surface morphologies and electrical properties of SiC epitaxial layers grown with varying a SiC/Al ratio in a SiC source powder during the sublimation growth using the CST method. The surface morphology was dramatically changed with varying the SiC/Al ratio. When the SiC/Al ratio of 90/1 was used, the step bunching was not observed in this magnification and the ratio of SiC/Al is an optimized range to grow of p-type SiC epitaxial layer. It was confirmed that the acceptor concentration of epitaxial layer was continuously decreased with increasing the SiC/Al ratio. 4H-SiC MESFETs haying a micron-gate length were fabricated using a lithography process and their current-voltage performances were characterized. It was confirmed that the increase of the negative voltage applied on the gate reduced the drain current, showing normal operation of FET device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.4
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• pp.213-217
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• 2015

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.12
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• pp.1381-1388
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• 2015

The smartwork is future-oriented working environment that allows us to engage in work anytime, anywhere conveniently and efficiently by utilizing information and communication technologies in a variety of locations and mobile environments. We proposed a smartwork platform to support the efficient housing management for small housing management companies. Our systems interwork in real time with smart mobile devices and SNS to support high quality housing service for tenants and rental operators. In this paper, we describe real-time complaint handling service using SNS which is a part of smartwork platform for the efficient housing management.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.5
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• pp.657-664
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• 2011

This paper proposes the revised ASCII code. The study started with consideration whether the ASCII code is proper or not in the side of the transmission efficiency in data communications. In data communications, when the consecutive "0" bits from the information devices input into the line coder, its consecutive "0" bits are scrambled to the predetermined patterns not to the consecutive "0" signal. The paper used to study with the statistical data for the frequency of the letters of the alphabets and the proposed rule of characters coding in reference. As a result of the study, when the proposed ASCII code is applied, the operation efficiency of the scrambler in the line coder is improved upto average 30%.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.12-16
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• 2009

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5{\times}10^{14}cm^{-3}$, size of $600{\um}m^2$ with $4.5\;{\Omega}$, and off-state leakage current below $50{\mu}A$. We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.