• 제목/요약/키워드: Electrical Field Optimization

검색결과 228건 처리시간 0.024초

송전선로용 고전압 절연체의 최적 형상에 대한 유한요소 해석 (Finite Element Analysis for the Optimal Shape of the High Voltage Insulator for Power Transmission Lines)

  • 김태용;산얄 심피;라벨로 마데우스;이준신
    • 한국전기전자재료학회논문지
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    • 제35권1호
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    • pp.66-71
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    • 2022
  • The insulator used for the transmission line is a device that is bonded with a cap, pin, ceramic, and cement to withstand insulation capacity and mechanical load. The insulator design can help to reduce the dispersion of the electric field; thus, the optimization of today's design, especially as demanded power grows, is critical. The designs of four manufacturers were used to perform a comparative analysis. Under dry circumstances of the new product, an electric field distribution study was done with no pollutants attached. Manufacturer D's design has the best voltage uniformity of 24.33% and the arc length of 500 mm or more. Manufacturer C's design has an equalizing voltage of more than 2% higher than that of other manufacturers. The importance of the design of the insulator and the number of connections according to the installation conditions is very efficient for transmission lines that will increase in the future.

수치해석을 이용한 PCB에서 전자계 분포의 최적화 (Optimization of Electromagnetic Field on PCB by Using Numerical Analysis)

  • 장인범;이찬오;김진사;정일형;이준웅
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1996년도 하계학술대회 논문집 C
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    • pp.1485-1488
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    • 1996
  • This paper presents a method for analyzing electromagnetic field of planar microwave structures, which is based on Finite Element Method and optimizes structure of microstripline on Printed Circuit Board.

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별도전원으로 여자되는 팬케이크 권선형 고온초전도 마그넷의 제작과 특성 시험 (Fabrication and Test Results of an HTS Magnet with Pancake Windings Excited by Multiple Power Sources)

  • 이광연;강명훈;이용석;이희준;차귀수
    • 전기학회논문지
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    • 제57권3호
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    • pp.384-389
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    • 2008
  • The cental magnetic field of an HTS magnet consisting of pancake windings can be increased if the magnet is excited by multiple power sources. Multiple power sources enable all pancake windings to conduct their critical currents. The HTS magnet consisting of pancake windings was excited by separate power sources in this paper. Critical currents of each pancake winding were determined by using optimization technique. Fabrication of the BSCCO magnet consisting of 10 pancake windings is described and test results of the BSCCO magnet are given. Central magnetic field and perpendicular magnetic field of the magnet excited by multiple power sources were compared with those of the magnet excited by a single power source.

초전도에너지 저장장치의 운전주기에 따른 최적교류손실 결정에 관한 연구 (Optimum AC losses Determination for Duty Cycle of Superconductive Magnetic Energy Storage)

  • Hwang, Seuk-Yong
    • 대한전기학회논문지
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    • 제39권7호
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    • pp.653-667
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    • 1990
  • Superconductor is consolidated, for required current capacity, with proper numbers of basic strands which are multifilamentary composites. Althouth superconductors are perfectly loss-free under DC conditions of current and field, AC losses occur under time-varying condition of the current and field. The AC losses are a controllable inherent characteristics of supercondectors. The AC losses dependent on the changing rate of current and field can be reduced by reducing the filament diameter. On the other hand, finer filament results in manufacturing cost increase. Therefore, in this paper optimization technique of superconductor for SMES is proposed from the viewpoint of AC loss reduction and manufacturing cost increase. The case study shows that the technique can be effectively used for the design of superconductor for SMES, appreciating the influence of various parameters related to superconductor itself and operating condition of SMES. As a result of the case study, it is confirmed that the technique is more effective for the design of superconductor for SMES for electric power power system stabilization rather then SMES for energy storage.

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전기영동전착에서 YBCO 초전도 후막의 인가전계 영향 (Effect of applied Field on YBCO Superconductor in EPD Method)

  • 소대화;전용우;최성재;박정철
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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    • pp.63-66
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    • 2003
  • The electrophoretic deposition method has the advantage of relatively few fabrication facilities and simple process procedure as well as the economical and technical merit of allowing various forms of deposition and easy control of deposition thickness and wire length. A study, especially electric field and additive, on the optimization method to increase the density of particles and uniformity of their orientation have been performed to overcome the cracking and the porosity problems in the fabricated superconductor.

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유전율 이방성이 양인액정을 이용한 Fringe-Field 구동형 수평배향된 단일갭 반투과형 디스플레이 (Homogeneous Aligned Single Gap Transflective Display driven by Fring-field using a Liquid Crystal with Positive Dielectic Anisotropy)

  • 임영진;최민오;이승희
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2005년도 춘계학술대회 논문집 디스플레이 광소자 분야
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    • pp.54-57
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    • 2005
  • We have designed a single gap transflective liquid crystal display (LCD) driven by a fringe electric field, in which the +LC (${\Delta}{\varepsilon}$=7.4, rubbing angle= $80^{\circ}$) is homogeneously aligned in the initial state. This device is a problem that the voltage-dependent transmittance and reflectance curves do not match each other. Thus a dual driving circuit is required. This study shows that optimization of the rubbing angle in the transmissive and reflective regions solves this problem so that the transflective display with a single cell gap and single gamma curve for reflective and transmissive region is possible.

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Toward Optimal FPGA Implementation of Deep Convolutional Neural Networks for Handwritten Hangul Character Recognition

  • Park, Hanwool;Yoo, Yechan;Park, Yoonjin;Lee, Changdae;Lee, Hakkyung;Kim, Injung;Yi, Kang
    • Journal of Computing Science and Engineering
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    • 제12권1호
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    • pp.24-35
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    • 2018
  • Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

3.3kV SiC MOSFET 설계 및 제작을 위한 JFET 및 FLR 최적화 연구 (A Study on JFET and FLR Optimization for the Design and Fabrication of 3.3kV SiC MOSFET)

  • 강예환;이현우;구상모
    • 반도체디스플레이기술학회지
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    • 제22권3호
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    • pp.155-160
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    • 2023
  • The potential performance benefits of Silicon Carbide(SiC) MOSFETs in high power, high frequency power switching applications have been well established over the past 20 years. In the past few years, SiC MOSFET offerings have been announced by suppliers as die, discrete, module and system level products. In high-voltage SiC vertical devices, major design concerns is the edge termination and cell pitch design Field Limiting Rings(FLR) based structures are commonly used in the edge termination approaches. This study presents a comprehensive analysis of the impact of variation of FLR and JFET region on the performance of a 3.3 kV SiC MOSFET during. The improvement in MOSFET reverse bias by optimizing the field ring design and its influence on the nominal operating performance is evaluated. And, manufacturability of the optimization of the JFET region of the SiC MOSFET was also examined by investigating full-map electrical characteristics.

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로봇 임베디드 시스템에서 리튬이온 배터리 잔량 추정을 위한 신경망 프루닝 최적화 기법 (Optimized Network Pruning Method for Li-ion Batteries State-of-charge Estimation on Robot Embedded System)

  • 박동현;장희덕;장동의
    • 로봇학회논문지
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    • 제18권1호
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    • pp.88-92
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    • 2023
  • Lithium-ion batteries are actively used in various industrial sites such as field robots, drones, and electric vehicles due to their high energy efficiency, light weight, long life span, and low self-discharge rate. When using a lithium-ion battery in a field, it is important to accurately estimate the SoC (State of Charge) of batteries to prevent damage. In recent years, SoC estimation using data-based artificial neural networks has been in the spotlight, but it has been difficult to deploy in the embedded board environment at the actual site because the computation is heavy and complex. To solve this problem, neural network lightening technologies such as network pruning have recently attracted attention. When pruning a neural network, the performance varies depending on which layer and how much pruning is performed. In this paper, we introduce an optimized pruning technique by improving the existing pruning method, and perform a comparative experiment to analyze the results.

전력반도체 고내압 특성 향상을 위한 필드링 최적화 연구 (A Study on the Field Ring of High Voltage Characteristics Improve for the Power Semiconductor)

  • 남태진;정은식;김성종;정헌석;강이구
    • 한국전기전자재료학회논문지
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    • 제25권3호
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    • pp.165-169
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    • 2012
  • Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.