• Journal of the Korean Society of Safety
• /
• v.15 no.4
• /
• pp.62-68
• /
• 2000

Static electricity in electronics manufacturing plants causes the economic loss, yet it is one of the least understood and least recognized effects haunting the industry today. Today's challenge in semiconductor devices is to achieve greater functional density pattern and to miniaturize electronic systems of being more fragile by electrostatic discharges(ESD) phenomena. As the use of automatic handling equipment for static-sensitive semiconductor components is rapidly increased, most manufacturers need to be more alert to the problem of ESD. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the static-sensitive devices. To evaluate the ESD hazards by charged human body and devices, in this paper, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated and the voltage to cause electronic component failures is investigated by field-induced charged device model(FCDM) tester. The FCDM simulator provides a fast and inexpensive test that faithfully represents ESD hazards in plants. Also the results obtained in this paper can be used for the prevention of semiconductor failure from ESD hazards.

• Journal of the Korean Society of Safety
• /
• v.17 no.4
• /
• pp.94-100
• /
• 2002

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipments need to be more alert to the problem of electrostatic discharges(ESD). In order to analyze damage characteristics of semiconductor device damaged by ESD, this study adopts a new charged-device model(CDM), field-induced charged model(FCDM) simulator that is suitable for rapid, routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. High voltage applied to the device under test is raised by the field of non-contacting electrodes in the FCDM simulator, which avoids premature device stressing and permits a faster test cycle. Discharge current and time are measured and calculated. The characteristics of electrostatic attenuation of domestic semiconductor devices are investigated to evaluate the ESD phenomena in the semiconductors. Also, the field charging mechanism, the device thresholds and failure modes are investigated and analyzed. The damaged devices obtained in the simulator are analyzed and evaluated by SEM. The results obtained in this paper can be used to prevent semiconductor devices form ESD hazards and be a foundation of research area and industry relevant to ESD phenomena.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.1
• /
• pp.1-6
• /
• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.36-46
• /
• 2010

In multi-GHz RF ICs and high-speed digital interfaces, ESD protection devices introduce considerable parasitic capacitance and resistance to inputs and outputs, thereby degrading the RF performance, such as input/output matching, gain, and noise figure. In this paper, the impact of ESD protection devices on the performance of RF ICs is investigated and design methodologies to minimize this impact are discussed. With RF and ESD test results, the 'RF/ESD co-design' method is discussed and compared to the conventional RF ESD protection method which focuses on minimizing the device size.

• Journal of the Korean Society of Safety
• /
• v.16 no.2
• /
• pp.57-62
• /
• 2001

In order to analyze the mechanism of semiconductor device damages by ESD, this paper adopts a new charged-device model(CDM), field-induced charged nudel(FCDM), simulator that is suitable for rapid routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. The high voltage applied to the device under test is raised by the fie]d of non-contacting electrodes in the FCDM simulator. which avoids premature device stressing and permits a faster test cycle. Discharge current md time are measured and calculated The FCDM simulator places the device at a huh voltage without transferring charge to it, by using a non-contacting electrode. The only charge transfer in the FCMD simulator happens during the discharge. This paper examine the field charging mechanism, measure device thresholds, and analyze failure modes. The FCDM simulator provides a Int and inexpensive test that faithfully represents factory ESD hazards. The damaged devices obtained in the simulator are analyzed and evaluated by SEM Also the results in this paper can be used for to prevent semiconductor devices from ESD hazards.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.54 no.3
• /
• pp.109-113
• /
• 2005

It has been reported that the failure phenomenon and variation of electrical characteristic due to the effect of electrostatic discharge(ESD) in silicon devices. But we had fess reports about the phenomenon due to the ESD in the compound semiconductors. So there are a lot of difficulty to the phenomenon analysis and to select the protection method of main circuits or the devices. It has not been reported that the relation between the ESD stress and GaN devices, which is remarkable to apply the operation in high temperature and high voltage due to the superior material characteristic. We studied that the characteristic variation of the AlGaN/GaN HEMT current, the leakage current, the transconductance(gm) and the failure phenomenon of device due to the ESD stress. We have applied the ESD stress by transmission line pulse(TLP) method, which is widely used in ESD stress experiments, and observed the variation of the electrical characteristic before and after applying the ESD stress. The on-current trended to increase after applying the ESD stress. The leakage current and transconductance were changed slightly. The failure point of device was mainly located in middle and edge sides of the gate, was considered the increase of temperature due to a leakage current. The GaN devices have poor thermal characteristic due to usage of the sapphire substrate, so it have been shown to easily fail at low voltage compared to the conventional GaAs devices.

• Journal of IKEEE
• /
• v.13 no.1
• /
• pp.19-29
• /
• 2009

For two input ESD protection schemes utilizing the NMOS protection device or the lvtr_thyristor protection device, which is suitable for high-frequency CMOS ICs, we attempt an in-depth comparison study on the HBM ESD protection level in terms of lattice heating inside the protection devices and the peak voltage applied to the gate oxides in the input buffer through DC, mixed-mode transient, and AC analyses utilizing the 2-dimensional device simulator. For this purpose, we suggest a method for the equivalent circuit modeling of the input HBM test environment for the CMOS chip equipped with the input ESD protection circuit. And by executing mixed-mode simulations including up to four protection devices and analyzing the results for five different test modes, we attempt a detailed analysis on the problems which can be occurred in a real HBM test. In this procedure, we explain about the strength and weakness of the two protection schemes as an input protection circuit for high-frequency ICs, and suggest guidelines relating to the design of the protection devices.

• Journal of the Korean Society of Safety
• /
• v.14 no.3
• /
• pp.69-77
• /
• 1999

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipment need to be more alert to the problem of electrostatic discharges(ESD). Semiconductor devices such as IC, LSI, VLSI become a high density pattern of being more fragile by ESD phenomena. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the electrostatic discharge sensitive devices. Accordingly, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated to evaluate the ESD phenomina in the semiconductors in this paper. The required data are obtained by Static Honestmeter. Also The results in this paper can be used for the prevention of semiconductor failure by ESD.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.4
• /
• pp.75-87
• /
• 2010

For two input-protection schemes suitable for RF ICs utilizing the thyristor and diode protection devices, which can be fabricated in standard CMOS processes, we attempt an in-depth comparison on HBM ESD robustness in terms of lattice heating inside protection devices and peak voltages developed across gate oxides in input buffers, based on DC, mixed-mode transient, and AC analyses utilizing a 2-dimensional device simulator. For this purpose, we construct an equivalent circuit for an input HBM test environment of a CMOS chip equipped with the input ESD protection circuits, which allows mixed-mode transient simulations for various HBM test modes. By executing mixed-mode simulations including up to six active protection devices in a circuit, we attempt a detailed analysis on the problems, which can occur in real tests. In the procedure, we suggest to a recipe to ease the bipolar trigger in the protection devices and figure out that oxide failure in internal circuits is determined by the junction breakdown voltage of the NMOS structure residing in the protection devices. We explain the characteristic differences of two protection schemes as an input ESD protection circuit for RF ICs, and suggest valuable guidelines relating design of the protection devices and circuits.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.6
• /
• pp.797-801
• /
• 2014

This research presented the concept of employing the punch-through diode triggered SCRs (PTTSCR) for low voltage ESD applications such as transient voltage suppression (TVS) devices. In order to demonstrate the better electrical properties, various traditional ESD protection devices, including a silicon controlled rectifier (SCR) and Zener diode, were simulated and analyzed by using the TCAD simulation software. The simulation result demonstrates that the novel PTTSCR device has better performance in responding to ESD properties, including DC dynamic resistance and capacitance, compared to SCR and Zener diode. Furthermore, the proposed PTTSCR device has a low reverse leakage current that is below $10^{-12}$ A, a low capacitance of $0.07fF/mm^2$, and low triggering voltage of 8.5 V at $5.6{\times}10^{-5}$ A. The typical properties couple with the holding voltage of 4.8 V, while the novel PTTSCR device is compatible for protecting the low voltage, high speed ESD protection applications. It proves to be good candidates as ultra-low capacitance TVS devices.