• Journal of Power Electronics
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• 제16권3호
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• pp.1036-1045
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• 2016

This paper presents a novel control strategy for passive output filter reduction using an active output filter. The proposed method achieves the dual-function of regulating the output voltage ripple and output voltage variation during load transients. The novel control strategy allows traditional simple voltage controllers to be used, without requiring the expensive current sensors and complex controllers used in conventional approaches. The proposed method is verified with results from a 125-W forward converter.

• 전기전자학회논문지
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• 제26권2호
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• pp.271-279
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• 2022

본 논문은 플로팅 커패시터를 갖는 이중 인버터의 향상된 데드 타임 보상 기법을 제안한다. 플로팅 커패시터를 갖는 이중 인버터는 2-레벨 단일 인버터보다 전력 반도체가 6개가 추가된다. 전력 반도체의 수가 증가로 이중 인버터의 출력 전압은 추가된 전력 반도체의 도통 전압만큼 감소되며 출력 전류 품질은 전력 반도체에 의한 전압 강하와 데드 타임에 의해 저하된다. 본 논문에서 제안하는 기법은 이중 인버터의 데드 타임 및 전력 반도체의 도통 전압을 보상하여 전류 품질을 개선하고 추가적인 대역통과 필터를 이용한 고조파 보상 기법을 통해 데드 타임과 도통 전압 보상에 대한 오차를 추가 보상한다.

• Journal of electromagnetic engineering and science
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• 제17권3호
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.129-131
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• 2006

This paper presents a new ZVS-PWM high frequency inverter. The ZVS operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. The operating principle and the operating characteristics of the new high frequency circuit treated here are illustrated and evaluated on the basis of simulation results. It was examined that the complete soft switching operation can be achieved even for low power setting ranges by introducing the high frequency dual duty cycle control scheme. In the proposed high frequency inverter treated here, the dual mode pulse modulation control strategy of the asymmetrical PWM in the higher power setting ranges and the lower power setting ones, the output power of this high frequency inverter could introduce in order to extend soft switching operation ranges. Dual duty cycle is used to provide a wide range of output power regulation that is important in many high frequency inverter applications. It is more suitable for induction heating applications the operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

• Journal of electromagnetic engineering and science
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• 제13권2호
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• pp.93-103
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• 2013

This paper presented a novel approach for the design of a tunable dual-band bandpass filter (BPF) with independently tunable passband center frequencies and bandwidths. The newly proposed dual-band filter principally comprised two dual-mode single band filters using common input/output lines. Each single BPF was realized using a varactor-loaded transmission line resonator. To suppress the harmonics over a broad bandwidth, a defected ground structure was used at the input/output feeding lines. From the experimental results, it was found that the proposed filter exhibited the first passband center frequency tunable range from 1.48 to 1.8 GHz with a 3-dB fractional bandwidth (FBW) variation from 5.76% to 8.55%, while the second passband center's frequency tunable range was 2.40 to 2.88 GHz with a 3-dB FBW variation from 8.28% to 12.42%. The measured results of the proposed filters showed a rejection level of 19 dB up to more than 10 times the highest center frequency of the first passband.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• 한국전자파학회논문지
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• 제25권3호
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• pp.376-379
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• 2014

본 논문은 910 MHz와 2.45 GHz 대역에서 동작하는 RFID 트랜시버용 전력증폭기를 설계 및 제작하였다. 제안된 이중 대역 전력증폭기는 집중정수 소자로 구현된 910 MHz 대역의 정합 회로와 분포정수 소자로 구현된 2.45 GHz 대역의 정합 회로로 구성되며, 두 대역의 격리를 위하여 910 MHz 대역에 대하여 대역 제거 필터(band rejection filter)로 동작하고, 2.45 GHz 대역에서는 대역 통과 필터(band pass filter)로 동작하는 ${\lambda}/2$ 직렬 마이크로스트립 전송 선로로 구성되어 있다. 제작된 이중 대역 전력증폭기는 910 MHz와 2.45 GHz에서 이득이 각각 8 dB와 1.5 dB를 나타냈으며, 입력 전력 10 dBm을 인가하여 얻은 출력 전력은 두 대역 모두 20 dBm을 얻었다.

• Journal of Welding and Joining
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• 제26권2호
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• pp.85-91
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• 2008

In general, the quality of a welding process tends to vary with depending on the work environment or external disturbances. Hence, in order to achieve the desirable quality of welding, we should have the optimal welding condition that is not significantly affected by these changes in the environment or external disturbances. In this study, we used a dual response surface method in consideration of both the mean output variables and the standard deviation in order to optimize the V-groove arc welding process. The input variables for GMA welding process with the dual response surface are welding voltage, welding current and welding speed. The output variables are the welding quality function using the shape factor of bead geometry. First, we performed welding experiment on the interested area according to the central composite design. From the results obtained, we derived the regression model on the mean and standard deviation between the input and output variables of the welding process and then obtained the dual response surface. Finally, using the grid search method, we obtained the input variables that minimize the object function which led to the optimal V-groove arc welding process.

• 대한전자공학회논문지TC
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• 제47권2호
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• pp.56-61
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• 2010

본 논문에서는 단일 FET와 composite right/left-handed (CRLH) 전송선을 이용하여 2.14GHz/5.2GHz 이중대역 고효율 전력 증폭기를 설계 구현하였다. 전송선로를 이용하여 초기의 정합값을 적절히 이동시켜 하나의 능동소자로 2.14GHz/5.2GHz의 이중대역에서 동작되는 전력증폭기를 설계하였다. 이중 대역에서 모든 고조파 성분을 조절하는 것은 매우 어렵기 때문에, CRLH 전송 선로를 이용하여 이중 대역에서 고효율 특성을 얻도록 오직 2차, 3차 고조파 성분만을 조절하였다. 또한, 이중 대역에서의 출력특성이 균형을 이루도록 하였다. 전력증폭기의 측정된 출력 전력은 각각 2.14 GHz에서 28.56 dBm, 5.2 GHz에서 29 dBm이다. 이 지점에서 얻은 전력 효율, PAE는 2.14 GHz에서 65.824 %, 5.2 GHz에서 69.86 %이다.