• 한국통신학회논문지
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• 제26권12C호
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• pp.255-260
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• 2001

본 논문에서는 새로운 locking 알고리즘을 사용하여 저전력의 특정을 가지면서 locking 속도가 빠른 Register Controlled DLL(Delay-Locked Loop)을 설계하였다. Locking 속도의 향상을 위해 제안한 알고리즘은 coarse와 fine controller를 각각 동작시키는 것으로, phase detector에서 출력되는 up/down 신호를 먼저 coarse controller에 인가하여 외부 클럭과 내부 클럭의 큰 위상차를 줄이고, coarse controller를 고정시킨 상태에서 up/down 신호를 fine controller에 인가하여 미세 지연 시간을 조정하도록 하는 것이다. 또한 제안한 DLL은 dual controller를 사용하지만 locking 동작시 한 개의 controller만 동작하므로 소비 전력을 줄일 수 있었으며 lock indicator를 사용하여 좋은 지터 특성을 보였다. 제안한 DLL은 0.6 $\mu\textrm{m}$ CMOS 공정 파라메타를 이용하여 설계하였고, SPICE 모의실험결과 50 MHz에서 200MHz가지 동작하였다. 200MHz 동작시 소비되는 전류는 15mA이며 모든 주파수에서 7 주기 이내에 locking 되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.