• International Journal of Control, Automation, and Systems
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• v.5 no.1
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• pp.104-109
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• 2007

This paper is about a redundancy management system design for the Smart UAV(unmanned aerial vehicle) which utilizes the tilt..rotor mechanism. In order to meet the safety requirement on the PLOC(probability of loss of control) of $1.7{\times}10^{-5}$ per flight hour for FCS (flight control system) failures, a digital FCS is mechanized with a dual redundant structure. A fault detection system which is composed of a CCM(cross channel monitor) and analytic redundancy using the Kalman filtering is designed, and its effectiveness is evaluated through experiments. A threshold level and persistence count for managing redundant sensors are designed based on the statistical analysis of the FCS sensors. To increase the survivability of the UAV after the loss of critical sensors in the SAS(stability augmentation system) and to provide reference information for a tie-breaking condition at which an ILM(in-line monitor) cannot distinguish the faulty channel between two operating ones, the Kalman filter approach is investigated.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.3
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• pp.119-125
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• 2014

Echo cancellation is required for a dual-duplex high speed communication such as digital subscriber line(DSL), in order to allow each individual loop to operate in a full duplex fashion. Echo cancellation was one of the most difficult aspects of DSL design, requiring high linearity and total echo return loss in excess of 70 dB. For a long and rapidly changing echo response, if the echo is cancelled by an adaptive echo canceller, the echo canceller needs more taps and its performance is decreased. But if the response is divided into several responses, which response is estimated by a adaptive digital filter and combined, the computation complexities are decreased and the performance is increased. Therefore, the adaptive multi-stage echo canceller is proposed to decrease the computation complexity and increase the performance of echo return loss, in which the echo canceller is composed of several stage echo canceller estimating each divided echo response. Through computer simulations, this multi-stage echo canceller is verified to have merits for high speed communications such as DSL application.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1B
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• pp.183-192
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• 2000

In this paper, the dual looped CMOS PLL with 3-250MHz input locking range at a single 13.3V is designed. This paper proposed a new PLL architecture with a current pumping algorithm to improve voltage-to-frequencylinearity of VCO(Voltage Controlled Oscillator). The designed VCO operates at a wide frequency range of75.8MHz-lGHz with a high linearity. Also, PFD(Phase frequency Detector) circuit preventing voltage fluctuation of the charge pump with loop filter circuit under the locked condition is designed. The simulation results of the PLL using 0.6 um N-well single poly triple metal CMOS technology illustrate a locking time of 3.5 us, a power dissipation of 92mW at 1GHz operating frequency with 125MHz of input frequency. Measured results show that the phase noise of VCO with V-I converter is -100.3dBc/Hz at a 100kHz offset frequency.