• 한국전자파학회논문지
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• 제14권8호
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• pp.839-844
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• 2003

위성 중계기의 무게와 부피를 최소화 하기 위하여 입력 멀티플렉서 및 출력 멀티플렉서에 사용하는 채널 필터는 이중모드 도파관 필터를 많이 사용한다. 또한 입력 멀티플렉서는 일반적으로 채널이 서로 독립적이기 때문에 이에 사용하는 채널 필터는 이중종단형으로 설계하며, 매니폴드(manifold) 형태의 출력 멀티플렉서의 경우 채널 필터는 단일종단형으로 설계한다. 본 논문에서는 위성 중계기에 많이 적용되는 단일종단 및 이중종단 이중모드 도파관 필터의 튜닝 방법에 관하여 기술하였다. 필터의 튜닝은 한쪽면이 단락된 더미 공동(dummy cavity)을 이용하며, 측정된 반사계수의 위상 응답을 계산된 이론치에 정합시키는 과정으로 튜닝을 진행한다. 이러한 튜닝방법을 4차 이중종단 이중모드 타원응답 필터와 6차 단일종단 이중모드 타원응답 필터에 적용하여 튜닝함으로써 제안한 튜닝방법의 유용성을 확인하였다.

• 한국통신학회논문지
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• 제34권9C호
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• pp.887-895
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• 2009

본 논문은 다중 안테나를 가진 릴레이가 설치된 다중-셀 다중-사용자 시스템에서 부분 채널 정보를 이용하여 기지국과 릴레이 간 협력적으로 전력을 할당하는 기법을 제안한다. 이중-흡 MISO (Multi-Input Single-Output) 릴레이 채널에서, 릴레이 채널 용량(end-to-end capacity)을 최대화하기 위해 홉 간 송신 전력을 채널 상태에 따라 동적으로 할당할 필요가 있다. 제안된 기법은 목표 릴레이의 평균 채널 이득과 인접 릴레이로부터의 원하는 채널과 간섭 채널의 송신 상관 행렬의 주요한 고유벡터의 상대적인 각도 차이를 고려하여 릴레이 송신 전력을 동적으로 할당한다. 상향-경계치 분석을 통해서 릴레이 채널 용량은 원하는 채널과 간섭 채널의 주요한 고유벡터의 상대적인 각도 차이가 직교가 될 때 최대가 됨을 이론적으로 증명하였다.

• Journal of electromagnetic engineering and science
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• 제16권3호
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• pp.164-168
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• 2016

A dual-band through-the-wall imaging radar receiver for a frequency-modulated continuous-wave radar system was designed and fabricated. The operating frequency bands of the receiver are S-band (2-4 GHz) and X-band (8-12 GHz). If the target is behind a wall, wall-reflected waves are rejected by a reconfigurable $G_m-C$ high-pass filter. The filter is designed using a high-order admittance synthesis method, and consists of transconductor circuits and capacitors. The cutoff frequency of the filter can be tuned by changing the reference current. The receiver system is fabricated on a printed circuit board using commercial devices. Measurements show 44.3 dB gain and 3.7 dB noise figure for the S-band input, and 58 dB gain and 3.02 dB noise figure for the X-band input. The cutoff frequency of the filter can be tuned from 0.7 MHz to 2.4 MHz.

• Journal of Electrical Engineering and Technology
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• 제11권1호
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.292-300
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• 2015

This paper proposes a high-efficiency, dual-mode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between $-40^{\circ}C$ and $140^{\circ}C$, the converter has variations in temperature of $0.5mV/^{\circ}C$ in the PWM mode and of $0.24mV/^{\circ}C$ in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class(Chip level) ESD protection circuit of a P-substrate Triggered SCR type with high robustness characteristics.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권10호
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of Power Electronics
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• 제15권2호
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• pp.309-318
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• 2015

This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current-direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an $85-265V_{rms}$ universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.

• 한국광학회지
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• 제29권1호
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• pp.28-31
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• 2018

본 논문에서는 이중 광 콜리메터 광학계와 바이메탈 엑추에이터를 이용한 가변 광감쇠기를 제안하고 구현하였다. 입력광섬유와 출력광섬유 사이의 광손실은 바이메탈에 부착된 반사거울의 기울어진 각으로 조절되어진다. 바이메탈은 열전소자(TEC)에 의해 가열되거나 냉각되며 이로 인해 구부림이나 펴짐으로 인하여 반사거울을 움직이게 한다. TEC에 가해지는 전기신호로 원하는 광감쇠량을 얻을 수 있다. 제작된 소자는 0.5 dB의 삽입손실, 0.2 dB의 편광의존성 손실 및 40 dB 이상의 가변변위를 보였다. 반응 시간은 약 5초였다.

• 대한임베디드공학회논문지
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• 제17권6호
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• pp.309-317
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• 2022

In this paper, we propose a machine learning-based copy-move forgery detection network with dual branches. Because the rotation or scaling operation is frequently involved in copy-move forger, the conventional convolutional neural network is not effectively applied in detecting copy-move tampering. Therefore, we divide the input into rotation-invariant and scaling-invariant features based on the wavelet coefficients. Each of the features is input to different branches having the same structure, and is fused in the combination module. Each branch comprises feature extraction, correlation, and mask decoder modules. In the proposed network, VGG16 is used for the feature extraction module. To check similarity of features generated by the feature extraction module, the conventional correlation module used. Finally, the mask decoder model is applied to develop a pixel-level localization map. We perform experiments on test dataset and compare the proposed method with state-of-the-art tampering localization methods. The results demonstrate that the proposed scheme outperforms the existing approaches.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 춘계종합학술대회
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• pp.142-145
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• 1999

본 논문에서는 이중 평면 패킷 스위치 구조를 가지는 이중 입력 /이중 스위칭 평면 구조(DQDP) 평면 선택 능력을 가진 DQDP(DQDP-PS) 구조, 출력 그룹 큐잉 능력을 가진 DQDP(DQDP-OGQ) 구조에 대한 지연 성능 분석을 연구하였다. 성능 분석을 통하여 랜덤 트래픽하에서는 거의 동일한 성능을 보이지만 버스트 트래픽 환경에서는 DQDP-PS와 DQDP-OGO 스위치만이 이상적인 출력 버퍼 패킷 스위치의 성능에 가까운 지연 특성을 얻을 수 있었다.