• Title/Summary/Keyword: Down converter

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Design of Second-order BPS Systems for the Cancellation of Multiple Aliasing (다중 aliasing 소거를 위한 2차 BPS 시스템의 설계)

  • Baek, Jein
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.3
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    • pp.162-170
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    • 2015
  • In the bandpass sampling (BPS), the sampling frequency is lower than the frequency of the signal to be sampled. In this method, the baseband spectrum can be directly obtained by the sampling operation. This makes the frequency down converter unnecessary as well as the receiver's circuit simpler. In the second-order BPS system, two sampling devices are used. When aliasing occurs due to the sampling operation, the aliased component can be cancelled by combining the two sampled signals. In this paper, it is presented a design method of the second-order BPS system when multiple interferences are simultaneously aliased to the signal component. The optimum phase of the interpolant filter is searched for maximizing the signal-to-interference ratio, and a practical formula for the suboptimal phase is derived in terms of the power spectrum profile of the BPS input. A computer simulation has been performed for the proposed second-order BPS system, and it has been shown that the signal-to-interference ratio can be increased by considering multiple aliasing.

Sigma Delta Decimation Filter Design for High Resolution Audio Based on Low Power Techniques (저전력 기법을 사용한 고해상도 오디오용 Sigma Delta Decimation Filter 설계)

  • Au, Huynh Hai;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.11
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    • pp.141-148
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    • 2012
  • A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

A study on the multiband interpolant filter for the second-order BPS system (2차 BPS 시스템을 위한 다중 대역 interpolant 필터 설계에 대한 연구)

  • Kim, Hyuk;Baek, Jein
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.69-72
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    • 2012
  • In the bandpass sampling(BPS), the sampling frequency is lower than the frequency of the RF(radio frequency) signal being sampled. In this method, the baseband spectrum directly appears by the sampling itself, so that it is not necessary to use any down converter, making the receiver's hardware simpler. The second-order BPS uses two identical BPS samplers operating with an offset timing to each other. By a processing with their two sampled signals, it can be possible to cancel the aliasing or interference component if any due to the bandpass sampling. The interpolant filter, which is to manipulate the phase characteristics of the sampled signal, affects the performance of the cancellation. In this paper, a multiband interpolant filter is introduced, with which multiple interference signals from multiple RF bands can be cancelled simultaneously. We suggest several phase characteristics for the interpolant filter and have evaluated their performances through computer simulations. It has been shown that the filter with a continuous phase function gives the better performance.

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Selective Harmonic Elimination in Multi-level Inverters with Series-Connected Transformers with Equal Power Ratings

  • Moussa, Mona Fouad;Dessouky, Yasser Gaber
    • Journal of Power Electronics
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    • v.16 no.2
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    • pp.464-472
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    • 2016
  • This study applies the selective harmonic elimination (SHE) technique to design and operate a regulated AC/DC/AC power supply suitable for maritime military applications and underground trains. The input is a single 50/60 Hz AC voltage, and the output is a 400 Hz regulated voltage. The switching angles for a multi-level inverter and transformer turns ratio are determined to operate with special connected transformers with equal power ratings and produce an almost sinusoidal current. As a result of its capability of directly controlling harmonics, the SHE technique is applicable to apparatus with congenital immunity to specific harmonics, such as series-connected transformers, which are specially designed to equally share the total load power. In the present work, a single-phase 50/60 Hz input source is rectified via a semi-controlled bridge rectifier to control DC voltage levels and thereby regulate the output load voltage at a constant level. The DC-rectified voltage then supplies six single-phase quazi-square H-bridge inverters, each of which supplies the primary of a single-phase transformer. The secondaries of the six transformers are connected in series. Through off-line calculation, the switching angles of the six inverters and the turns ratios of the six transformers are designed to ensure equal power distribution for the transformers. The SHE technique is also employed to eliminate the higher-order harmonics of the output voltage. A digital implementation is carried out to determine the switching angles. Theoretical results are demonstrated, and a scaled-down experimental 600 VA prototype is built to verify the validity of the proposed system.

A Study on the Development of Soil Moisture Measuring Unit (인공토조용(人工土槽用) 토양함수율(土壤含水率) 측정기(測程器) 개발(開發)에 관(關)한 연구(硏究))

  • Park, J.G.;Lee, S.K.;Rhee, J.Y.
    • Journal of Biosystems Engineering
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    • v.11 no.2
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    • pp.14-22
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    • 1986
  • This study was carried out to find a method which can be used to measure the soil moisture content of the soil bin exactly and quickly. And gypsum block is used as an instrument in measuring soil moisture content in the field of green house farming, etc.. However the characteristics of gypsum block, or the guide line of making gypsum block is not well introduced in Korea. So the information about gypsum block such as the density of gypsum, type of electrode, dimension of electrode, distance between electrodes, density of surrounding soil were included in this study and their effects on the relationship between soil moisture content and electrical resistance were investigated. The results of this study are as follows; 1. The grid type electrode was quicker in accessing the equilibrium condition and showed more sensitive response to the change of soil moisture content than the plate type electrode. 2. The longer the distance between the electrodes, the larger the electrical resistance, and the distance of 3 to 5 mm was recommended. 3. The larger the width of the electrode, the smaller the electrical resistance. However, there was no significance between the levels designed in this study. Considering the size of the gypsum block itself, the adaptible range of width may be 4 to 8 mm. 4. The higher the density of gypsum, the smaller the electrical resistance. And the block of lower density was broken down in the soil of higy moisture content. The optimum ratio of gypsum to water was 7:5. 5. The measuring system used in this study allowed simultaneous, multi-data acquisition. So this system using A/D converter can be applied to the measurement of soil moisture content of soil bin.

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A study on Light Tracking using Intel's 8080 microprocessor (INTEL 8080 microprocessor를 이용한 광추적에 관한 연구)

  • 이동렬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.10 no.1
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    • pp.1-10
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    • 1985
  • Solar energy has its advantages not to be interruped by anything, which is wing to not only limitlessness in its source but shortness in its wave. Availing of tha advantages, we can look forword to vast allication. This study whose aim is to raise the effectuality of it by means of chasing the source correctly, which is to be acheved by the circularty of sensor. The consequence has been gained by two sensors is amplified and transfered to TTL leveland becomes "INPUT DATA" of INTE 8080CPU. The INTEL 8080CPU whose system is machinated to give cotrol pulse to moter driving circuit has the source and the sensors placed correctly on the basis of the data. DC motor taskes the advantage not to be in need of UP/DOWN counter, which is defferent from stepping motor. The system is composed of light detector, A/C converter, INPUT Interface, INTEL 8080 CPU, OUTPUT Interface, notor driving circiut. We can give correct chase to light experimentally as far as an error is the space of 1.2.ce of 1.2.

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The Desing of GaAs MESFET Resistive Mixer with High Linearity (선형성이 우수한 GaAs MESFET 저항성 혼합기 설계)

  • 이상호;김준수;황충선;박익모;나극환;신철재
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.10 no.2
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    • pp.169-179
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    • 1999
  • In this paper, a GaAs MESFET single-ended resistive mixer with high linearity and isolation is designed. The bias voltage of this mixer is applied only gate of GaAs MESFET to use the channel resistance. The LO is applied the gate and the RF is applied the drain through 7-pole hairpin bandpass filter to obtain the proper isolation thru LO-RF. The IF is extracted from the source with short circuit and lowpass filter. Using extracted equivalent circuits for LO and RF, conversion loss is calculated and compared with result of harmonic balance analysis. Measured conversion loss of this S-band down converter mixer is 8.2~10.5dB by considering the measured 3.0~3.4dB RF 7-pole hairpin bandpass filter loss and IP3in is 26.5dBm at Vg=-0.85~-1.0V in distortion performance.

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Implementation of Wideband Low Noise Down-Converter for Ku-Band Digital Satellite Broadcasting (Ku-대역 광대역 디지탈 위성방송용 저 잡음하향변환기 개발)

  • Hong, Do-Hyeong;Lee, Kyung Bo;Rhee, Young-Chul
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.2
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    • pp.115-122
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    • 2016
  • In this paper, wideband Ku-band downconverter was designed to receiver digital satellite broadcasting. The low-nose downconverter was designed to form four local oscillator frequencies(9.75, 10, 10.75 and 11.3 GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75 GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select intermediate frequency bands by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64 dB, and the noise figure of low-noise amplifier was 0.7 dB, the P1dB of output signal 15 dBm, and the phase noise -85 dBc@10kHz at the band 1 carrier frequency of 9.75 GHz. The low noise block downconverter(LNB) for wideband digital satellite broadcasting designed in this paper can be used for global satellite broadcasting LNB.

Improved Load Sharing Rate in Paralleled Operated Lead Acid Batteries (납 축전지의 병렬운전시 부하분담률 개선)

  • 반한식;최규하
    • The Transactions of the Korean Institute of Power Electronics
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    • v.6 no.1
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    • pp.34-42
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    • 2001
  • A battery is the device that transforms the chemical energy into the direct-current electrical energy directly without a mechanical process. Unit cells are connected in series to obtain the required voltage, while being connected in parallel to organize capacity for load current and to decrease the internal resistance for corresponding the sudden shift of the load current. Because the voltage droop down in one set of battery is faster than in tow one, it amy result in the low efficiency of power converter with the voltage drop and cause the system shutdown. However, when the system being driven in parallel, a circular-current can be generated. The changing current differs in each set of battery because the system including batteries, rectifiers and loads is connected in parallel and it makes the charge voltage constant. It is shown that, as a result the new batteries are heated by over-charge and over-discharge, and the over charge current increases rust of the positive grid and consequently shortens the lifetime of the new batteries. The difference between the new batteries and old ones is the amount of internal resistance. In this paper, we can detect the unbalance current using the micro-processor and achieve the balance current by adjusting resistance of each set. The internal resistance of each set becomes constant and the current of charge and discharge comes to be balanced by inserting the external resistance into the system and calculating the change of internal resistance.

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Robustness Examination of Tracking Performance in the Presence of Ionospheric Scintillation Using Software GPS/SBAS Receiver

  • Kondo, Shun-Ichiro;Kubo, Nobuaki;Yasuda, Akio
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • v.2
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    • pp.235-240
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    • 2006
  • Ionospheric scintillation induces a rapid change in the amplitude and phase of radio wave signals. This is due to irregularities of electron density in the F-region of the ionosphere. It reduces the accuracy of both pseudorange and carrier phase measurements in GPS/satellite based Augmentation system (SBAS) receivers, and can cause loss of lock on the satellite signal. Scintillation is not as strong at mid-latitude regions such that positioning is not affected as much. Severe effects of scintillation occur mainly in a band approximately 20 degrees on either side of the magnetic equator and sometimes in the polar and auroral regions. Most scintillation occurs for a few hours after sunset during the peak years of the solar cycle. This paper focuses on estimation of the effects of ionospheric scintillation on GPS and SBAS signals using a software receiver. Software receivers have the advantage of flexibility over conventional receivers in examining performance. PC based receivers are especially effective in studying errors such as multipath and ionospheric scintillation. This is because it is possible to analyze IF signal data stored in host PC by the various processing algorithms. A L1 C/A software GPS receiver was developed consisting of a RF front-end module and a signal processing program on the PC. The RF front-end module consists of a down converter and a general purpose device for acquiring data. The signal processing program written in MATLAB implements signal acquisition, tracking, and pseudorange measurements. The receiver achieves standalone positioning with accuracy between 5 and 10 meters in 2drms. Typical phase locked loop (PLL) designs of GPS/SBAS receivers enable them to handle moderate amounts of scintillation. So the effects of ionospheric scintillation was estimated on the performance of GPS L1 C/A and SBAS receivers in terms of degradation of PLL accuracy considering the effect of various noise sources such as thermal noise jitter, ionospheric phase jitter and dynamic stress error.

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