• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2000년도 하계학술대회 논문집
• /
• pp.790-793
• /
• 2000

We have fabricated good quality superconducting YBa$_2$Cu$_3$$O_{7-x}$(YBCO) thin films on Hastelloy(Ni-Cr-Mo alloys) metallic substrates with CeO$_2$and BaTiO$_3$buffer layers in-situ by pulsed laser deposition in a multi-target processing chamber. YBCO film with CeO$_2$ single buffer layer shows T$_{c}$ of 71.64 K and the grain size less than 0.1 ${\mu}{\textrm}{m}$. When BaTiO$_3$is used as a single buffer layer, the grain size of YBCO is observed to be larger than that of YBCO/CeO$_2$by 200 times and the transition temperature of the film is enhanced to be about 84 K. CeO$_2$/BaTiO$_3$double buffer layer has been adopted to enhance the superconducting properties, which results in the enhancement of the critical temperature and the critical current density to be about 85 K and 8.4 $\times$ 10$^4$ A/cm$^2$ at 77 K, respectively mainly due to the enlargement of the grain size of YBCO film.ilm.

• Progress in Superconductivity
• /
• 제10권2호
• /
• pp.99-102
• /
• 2009

We report our development of the fabrication process of sub-micron scale $Al-AlO_x-Al$ tunnel junction by using electron-beam lithography and double-angle shadow evaporation technique. We used double-layer resist to construct a suspended bridge structure, and double-angle electron-beam evaporation to form a sub-micron scale overlapped junction. We adopted an e-beam insensitive resist as a bottom sacrificing layer. Tunnel barrier was formed by oxidation of the bottom aluminum layer between the bottom and top electrode deposition, which was done in a separate load-lock chamber. The junction resistance is designed and controlled to be 50 $\Omega$ to match the impedance of the transmission line. The junctions will be used in the broadband shot noise thermometry experiment, which will serve as a link between the electrical unit and the thermodynamic unit.

• 전자공학회논문지D
• /
• 제35D권6호
• /
• pp.46-53
• /
• 1998

저온 공정으로 제작되는 다결정 실리콘 박막 트랜지스터의 활성층을 이중 활성층(a-Si/a-SiN/sub x/)으로 제작하는 공정을 제안하고 다결정 실리콘 박막 트랜지스터를 제작하였다. 본 논문에서는 활성층의 아래쪽 실리콘 박막에 약간의 질소기를 첨가한 후 그 위에 순수한 비정질 실리콘 박막을 증착하여 엑시머 레이저의 에너지로 비정질 실리콘 박막을 결정화하여 사용하였다. 이중 활성층 (a-Si/a-SiN/sub x/)의 경우, 하부층의 NH₃/SiH₄ 유속비가 증가함에 따라, 상부 a-Si 층의 결정 성장이 촉진됨을 알 수 있었으나, n/sup +/ poly-SiN/sub x/ 층의 전도도 특성을 고려해 볼 때, NH₃/SiH₄ 유속비는 0.11의 상한치를 가짐을 알 수 있었다. 전계 방출 전류에 영향을 미치는 광학적 밴드갭의 경우, poly-Si 박막에 비해 증가하였으며, NH₃/SiH₄ 유속비가 0.11 이하에서도 0.1eV 정도의 증가를 보여, 이로 인하여 소자 제작시 전계 방출 전류가 억제될 것을 예상할 수 있다.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
• /
• pp.436-437
• /
• 2012

Double patterning technology (DPT) has been suggested as a promising candidates of the next generation lithography technology in FLASH and DRAM manufacturing in sub-40nm technology node. DPT enables to overcome the physical limitation of optical lithography, and it is expected to be continued as long as e-beam lithography takes place in manufacturing. Several different processes for DPT are currently available in practice, and they are litho-litho-etch (LLE), litho-etch-litho-etch (LELE), litho-freeze-litho-etch (LFLE), and self-aligned double patterning (SADP) [1]. The self-aligned approach is regarded as more suitable for mass production, but it requires precise control of sidewall space etch profile for the exact definition of hard mask layer. In this paper, we propose etch end point detection (EPD) in spacer etching to precisely control sidewall profile in SADP. Conventional etch EPD notify the end point after or on-set of a layer being etched is removed, but the EPD in spacer etch should land-off exactly after surface removal while the spacer is still remained. Precise control of real-time in-situ EPD may help to control the size of spacer to realize desired pattern geometry. To demonstrate the capability of spacer-etch EPD, we fabricated metal line structure on silicon dioxide layer and spacer deposition layer with silicon nitride. While blanket etch of the spacer layer takes place in inductively coupled plasma-reactive ion etching (ICP-RIE), in-situ monitoring of plasma chemistry is performed using optical emission spectroscopy (OES), and the acquired data is stored in a local computer. Through offline analysis of the acquired OES data with respect to etch gas and by-product chemistry, a representative EPD time traces signal is derived. We found that the SE-EPD is useful for precise control of spacer etching in DPT, and we are continuously developing real-time SE-EPD methodology employing cumulative sum (CUSUM) control chart [2].

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.149-149
• /
• 2010

The double-layer antireflection (DLAR) coatings have significant advantages over single-layer antireflection (SLAR) coatings. This is because they will be able to cover a broad range of the solar spectrum which would enhance the overall performance of solar cells. Moreover films deposited at high frequency are expected to show excellent and UV-stable passivation in the refractive index that we adopted. In this work, we present a novel DLAR coating using SiNx:H thin films with refractive indices 1.9 and 2.3 as the top and bottom layers. This approach is cost effective when compared to earlier DLAR coatings with two different materials. SiNx:H films were deposited by Plasma enhanced chemical vapor deposition (PECVD) technique using $SiH_4$, $NH_3$ and $N_2$ gases with flow rates 20~80sccm, 200sccm and 85 sccm respectively. The RF power, plasma frequency and substrate temperature for the deposition were 300W, 13.56 MHz and $450^{\circ}C$, respectively. The optimum thickness and refractive indices values for DLAR coatings were estimated theoretically using Macleod simulation software as 82.24 nm for 1.9 and 68.58 nm for 2.3 respectively. Solar cells were fabricated with SLAR and DLAR coatings of SiNx:H films and compared the cell efficacy. SiNx:H> films deposited at a substrate temperature of $450^{\circ}C$ and that at 300 W power showed best effective minority carrier lifetime around $50.8\;{\mu}s$. Average reflectance values of SLAR coatings with refractive indices 1.9, 2.05 and 2.3 were 10.1%, 9.66% and 9.33% respectively. In contrast, optimized DLAR coating showed a reflectance value as low as 8.98% in the wavelength range 300nm - 1100nm.

• Current Photovoltaic Research
• /
• 제5권2호
• /
• pp.63-67
• /
• 2017

Aluminum oxide ($Al_2O_3$) film deposited by atomic layer deposition (ALD) is known to supply excellent surface passivation properties on crystalline Si surface. The quality of passivation layer is important for high-efficiency silicon solar cell. double-layer structures have many advantages over single-layer materials. $Al_2O_3/SiN_X$ passivation stacks have been widely adopted for high- efficiency silicon solar cells. The first layer, $Al_2O_3$, passivates the surface, while $SiN_X$ acts as a hydrogen source that saturates silicon dangling bonds during annealing treatment. We explored the properties on passivation film of $Al_2O_3/SiN_X$ stack layer with changing the conditions. For the post annealing temperature, it was found that $500^{\circ}C$ is the most suitable temperature to improvement surface passivation.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.264-264
• /
• 2010

Single-walled carbon nanotubes (SWCNTs) were grown on a Si wafer by using thermal chemical vapor deposition (t-CVD). We investigated the effect of the catalyst deposition rate on the types of CNTs grown on the substrate. In general, smaller islands of catalyst occur by agglomeration of a catalyst layer upon annealing as the catalyst layer becomes thinner, which results in the growth of CNTs with smaller diameters. For the same thickness of catalyst, a slower deposition rate will cause a more uniformly thin catalyst layer, which will be agglomerated during annealing, producing smaller catalyst islands. Thus, we can expect that the smaller-diameter CNTs will grow on the catalyst deposited with a lower rate even for the same thickness of catalyst. The 0.5-nm-thick Fe served as a catalyst, underneath which Al was coated as a catalyst support as well as a diffusion barrier on the Si substrate. The catalyst layers were. coated by using thermal evaporation. The deposition rates of the Al and Fe layers varied to be 90, 180 sec/nm and 70, 140 sec/nm, respectively. We prepared the four different combinations of the deposition rates of the AI and Fe layers. CNTs were synthesized for 10 min by flowing 60 sccm of Ar and 60 sccm of $H_2$ as a carrier gas and 20 sccm of $C_2H_2$ as a feedstock at 95 torr and $810^{\circ}C$. The substrates were subject to annealing for 20 sec for every case to form small catalyst islands prior to CNT growth. As-grown CNTs were characterized by using field emission scanning electron microscopy, high resolution transmission electron microscopy, Raman spectroscopy, UV-Vis NIR spectroscopy, and atomic force microscopy. The fast deposition of both the Al and Fe layers gave rise to the growth of thin multiwalled CNTs with the height of ${\sim}680\;{\mu}m$ for 10 min while the slow deposition caused the growth of ${\sim}800\;{\mu}m$ high SWCNTs. Several radial breathing mode (RBM) peaks in the Raman spectra were observed at the Raman shifts of $113.3{\sim}281.3\;cm^{-1}$, implying the presence of SWCNTs (or double-walled CNTs) with the tube diameters 2.07~0.83 nm. The Raman spectra of the as-grown SWCNTs showed very low G/D peak intensity ratios, indicating their low defect concentrations.

• 동굴
• /
• 제75호
• /
• pp.49-54
• /
• 2006

Electrophoretic Deposition (EPD) is the most convenient technology to deposit natural or oxide powders of nonconductive materials in alcoholic suspension solution with adding electrolyte of iodine to form ceramic thick film on metal substrate under applied electric field with double electric layer between electrode and metal substrate. In this research work, the important parameters and technical ways were studied to form EPD thick films of typical oxide ceramics of Al2O3, YBCO and tourmaline powders.

• 한국표면공학회지
• /
• 제29권5호
• /
• pp.449-453
• /
• 1996

In order to improve EL performance, anthracene was doped into the 8-hydroxyquinoline-aluminum (Alq$^3$) light-emitting layer of organic double layered EL cells. The EL cells were fabricated on ITO glass substrates by vacuum deposition. Doping of anthracene to the light-emitting $Alq^3$layer was performed by means of co-evaporation. The doping concentration was changed in the range of 5 to 30 wt.%. It was confirmed that anthracene doping of appropriate concentration increased the available current density and brightness of the EL cells. Carrier mobility of the $Alq^3$ layer was measured by time of flight method. The influence of anthracene doping on the cell performance was discussed.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
• /
• pp.351.1-351.1
• /
• 2014

In this study, we prepared the solution-based In-Ga-Zn oxide thin film transistors (IGZO TFTs) of multistacked active layer and characterized the gate bias instability by measuring the change in threshold voltage caused by stacking. The solutions for IGZO active layer were prepared by In:Zn=1:1 mole ratio and the ratio of Ga was changed from 20% to 30%. The TFTs with multistacked active layer was fabricated by stacking single, double and triple layers from the prepared solutions. As the number of active layer increases, the saturation mobility shows the value of 1.2, 0.8 and 0.6 (). The electrical properties have the tendency such as decreasing. However when gate bias VG=10 V is forced to gate electrode for 3000 s, the threshold voltage shift was decreased from 4.74 V to 1.27 V. Because the interface is formed between the each layers and this affected the current path to reduce the electrical performances. But the uniformity of active layer was improved by stacking active layer with filling the hole formed during pre-baking so the stability of device was improved. These results suggest that the deposition of multistacked active layer improve the stability of the device.