• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.227-232
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• 1988

A semicustom VLSI design fo digital filters used in TDM/FDM transmultiplexer is described. A filter bank composed of only all-pass digital filter sections are implemented with the polyphase network. The use of all-pass filters as basic building blocks is shown to provide a trans-multiplexer structure that has low computational requirements, low quantization noise, and high modularity. The silicon compiler system is used to reduce the design time and to increase the credibility of designed filters. As a prototype, 1st and 2nd order all pass filter are designed, using CMOS N-well double metal technology. The chip sizes of first order filter and the second order filter are 2652 x 533\ulcorner\ulcorner 5334x4300\ulcorner\ulcorner respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.28-36
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• 1997

In this work, a highly linear video-speed CMOS current-mode digital-to-analog converter (DAC) is proposed. A newswitching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral nonlinearities (INL). The proposed DAC is designed to operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with degliching circuits developed in this work. The prototype dAC was implemented in a LG 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral nonlinearities are less than .+-. LSB and .+-.0.8LSB respectively. The DAC dissipates 75mW at a 3V single power supply and occupies a chip area of 2.4 mm * 2.9mm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.12
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Journal of Information Display
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• v.5 no.2
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• pp.1-5
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA ($240{\times}320$) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1324-1326
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• 2006

In this study, an integrated microelectrode array was fabricated on glass slide using microfabrication technology. Probe DNAs consisting of mercaptohexyl moiety at their 5-end were spotted on the gold electrode using micropipette or DNA arrayer utilizing the affinity between gold and sulfur. Cyclic voltammetry in 5mM ferricyanide/ferrocyanide solution at 100 mV/s confirmed the immobilization of probe DNA on the gold electrodes. When several DNAs were detected electrochemically, there was a difference between target DNA and control DNA in the anodic peak current values. It was derived from specific binding of Hoechst 33258 to the double stranded DNA due to hybridization of target DNA. It suggested that this DNA chip could recognize the sequence specific genes. It suggested that multichannel electrochemical DNA microarray is useful to develop a portable device for clinical gene diagnostic system.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Journal of the Korean Wood Science and Technology
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• v.17 no.4
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• pp.57-69
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• 1989

Roughage feeds were produced from Hyun-aspen (Populus alba $\times$ p. glandulosa) by steaming-defibration and steaming-explosion. The objectives of this work were to find proper conditions for the treatment of Hyun-aspen by analyzing the compositional change and digestibility and to investigate the change of physical properties of exploded woods. The results of this work were as follows; 1. The method of steaming-de fibration gave the best producing rate of feedstuffs when the chips were steamed (9kg/$cm^2$ under the pressure) for 10 minutes. The yield and the digestibility of feedstuffs were 84.2% and 38.1%, respectively. It is the merit of this method that feedstuffs manufactured by this method was uniformity in particle size, and facilities of fiberboard factory could be used directly, 2. For defibration of the chip by explosion, the proper condition was steamed under the pressure (20kg/$cm^2$) for 4 minutes. The yield and the digestibility of feedstuffs were 93.4% and 68.1%, respectively. The feedstuffs produced under these conditions had higher nutritional quality than rice straw and this method was considered as the best for making feedstuffs from Hyun-aspen chip. But it is defect that exploded feedstuffs was ununiformity in particle size and had unique odor. The physical properties of the feedstuffs were investigated by a light microscope and a TEM. The feedstuffs produced under the low pressure (20 kg/$cm^2$) still maintained the structure of fibers. However, the feedstuffs produced under the high pressure (28 kg/$cm^2$) resulted in higher de fib ration than these prepared under the low pressure. The highly defibrated feedstuffs recombined with solublized lignin. The crystallinity of feedstuffs was increased by 10% and micelle width increased double after treatment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• Journal of Sensor Science and Technology
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• v.5 no.4
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• pp.41-46
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• 1996

The Pd/Pt gate MISFET type hydrogen sensors, for detecting dissolved hydrogen gas in the transformer oil, were fabricated and their characteristics were investigated. These sensors including diffused resister heater and temperature monitoring diode were fabricated on the same chip by a conventional silicon process technique. The differential pair plays a role in minimizing the intrinsic voltage drift of the MISFET. To avoid the drift of the sensors induced by the hydrogen, the gate insulators of both FETs were constructed with double layers of silicon dioxide and silicon nitride. In order to eliminate the blister formation on the surface of the hydrogen sensing gate metal, Pt and Pd double metal layers were deposited on the gate insulator. The hydrogen response of the Pd/Pt gate MISFET suggests that the proposed sensor can detect the dissolved hydrogen in transformer oil with 40mV/10ppm of sensitivity and 0.14mV/day of stability.