• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.443-444
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• 2008

A double-balanced frequency up-converter using the Gilbert cell structure has been designed with the TSMC $0.18\;{\mu}m$ CMOS library. The frequency up-converter consists of a Mixer core and IF / LO balun. Frequency Up-converter exhibits a 3.4 dB conversion gain with a - 7.6 dBm $P_{1dB}$ for IF power of -10 dBm and LO power of 0 dBm inputs. It also exhibits 92.2 % modulation depth as a ASK modulator.

• Journal of electromagnetic engineering and science
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• v.4 no.1
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• pp.37-42
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• 2004

In this paper, LNB(low noise block) downconverter MMIC is designed for Ku-band satellite communication system using InGaP/GaAs HBT high linear process. Designed MMIC consists of low noise amplifier, double balanced mixer, and IF amplifier with a total chip area of 2.6${\times}$1.1 $\textrm{mm}^2$. Designed MMIC has the characteristics of over 37.5 ㏈ conversion gain, 14 ㏈ noise figure, ripple of 3 ㏈, and output-referred $P_{1dB}$TEX>(1 ㏈ compression power) of 2.5 ㏈m with total power dissipation of 3 V, 50 mA.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.311-320
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• 2008

In this paper, a 2.4 GHz low-voltage CMOS double-balanced down-conversion mixer using neutralization technique has been proposed and verified by circuit simulations and measurements. The grounded source structure was used for low-voltage operation. The neutralization technique was used to improve a conversion gain. The proposed mixer is fabricated in $0.25{\mu}m$ CMOS process for a 2.4 GHz wireless receiver. The mixer consumes 1.94 mW and gives conversion gain of 5.66 dB, input IP3 of 0.7 dBm and P1dB of -11.2 dBm at 1.5 V power supply. Measured results for the designed mixer show improved conversion gain of 2.86 dB over conventional mixer of grounded source structure.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.615-616
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• 2006

Nowadays, the need of multi-mode/multi-band transceiver is rapidly increasing, so we design a direct conversion RF front-end for multi-mode/multi-band receiver that support WCDMA/CDMA2000/WIBRO standard. It consists of variable gain reconfigurable LNA and single input double balanced Mixer and complementary differential LC Oscillator. The circuit is implemented in 0.18 um RF CMOS technology and is suitable for low-cost mode/multi-band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.110-115
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• 2000

A K-band GaAs MMIC receiver module has been developed using 0.15 ${\mu}{\textrm}{m}$ HEMT technology process. It incorporates two front end low noise amplifiers, a double balanced diode mixer, and filters. The RF input frequency ranges 20.1 to 21 GHz and the IF output 1.1 to 2 GHz. Test results show an overall conversion gain of more than 27 dB, and less than a 2.2 dB noise figure. The image-rejection ratio greater than 21 dB has been obtained. The isolation between RF and IF ports is better than 27 dB, and between LO and IF is more than 50 dB.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1508-1509
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• 2007

본 논문에서는 TSMC 0.18um공정을 이용한 무선통신 수신기용 직접변환 방식의 Double Balanced Mixer를 설계 하였다. 제안된 mixer는 current bleeding기법과 내부에 인덕터를 추가하여 기존의 Gilbert Cell구조의 mixer에 비해 변환 이득과 Flicker Noise특성을 향상 시켰다. 모의실험결과 2.45GHz에서 11dB의 변환이득을 나타내었으며 Flicker Noise의 corner frequency는 510kHz이고 이때 잡음특성은 10.8dB이다. 이 회로의 동작전압은 1.8V이며 소모 전력은 8.8mW이다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.894-897
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• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• Journal of Power Electronics
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• v.19 no.1
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• pp.134-145
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• 2019

A single-phase step-up five-level inverter topology with a new phase-shifted pulse width modulation (PS-PWM) strategy is proposed in this paper. When compared with conventional single-phase five-level inverter topologies, the proposed topology can realize multilevel inversion with a double step-up ratio, a reduced number of switching devices and self-balanced capacitor voltages. When compared with the conventional PS-PWM strategy, the new PS-PWM strategy can be implemented with one carrier reduced, which makes it much easier to implement in a digital signal processor (DSP) system. Experimental results have been presented to verify the effectiveness of the proposed inverter and the PS-PWM strategy.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.79-85
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• 2004

In this paper, the RF-ID system for ubiquitous tagging applications has been designed, fabricated and analysed. The RF-ID System consists of passive RF-ID Tag and Reader. The passive RF-ID tag consists of rectifier using zero-bias schottky diode which converts RF power into DC power, ID chip, ASK modulator using bipolar transistor and slot loop antenna. We suggest an ASK undulation method using a bipolar transistor to compensate the disadvantage of the conventional PIN diode, which needs large current Also, the slot loop antenna with wider bandwidth than that of the conventional patch antenna is suggested The RF-ID reader consist of patch array antenna, Tx/Rx part and ASK demodulator. We have designed the RF-ID System using EM and circuit simulation tools. According to the measured results, The power level of modulation signal at 1 m from passive RF-ID Tag is -46.76 dBm and frequency of it is 57.2 KHz. The transmitting power of RF-ID reader was 500 mW