• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.10-17
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• 2009

Nano-Electro-Mechanical MOSFET (NEMFET) using Double-Gate MOSFET (DGMOS) structure can efficiently control the short channel effect. Espatially, subthreshold current of depletion-mode Double-Gate NEMFET (Dep-DGNEMFET) decreases in the off-state due to the thin equivalent-oxide thickness. Analytical $t_gap$ vs. $V_g$ equation for Dep-DGNEMFET is derived and characteristics for different device structures are analyzed. Dep-DGNEMFET structure is optimized to satisfy ITRS criteria.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.163-168
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• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.7
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• pp.1074-1078
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• 2002

In this paper, we designed double gate(DG) MOSFET structure which has main gate(MG) and two side gates(SG). We have simulated using TCAD simulator U .WOSFET have the main gate length of %m and the side gate length of 70nm. Then, u'e have investigated the pinch-off characteristics, drain voltage is changed from 0V to 1.5V at VMG=1.5V and VSG=3.0V. In spite of the LMG is very small, we have obtained a very good pinch-off characteristics. Therefore, we know that the DG structure is very useful at nano scale.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.691-694
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• 2003

Density gradient method is used to analyze the quantum effect in MOSFET, Quantization effect in the poly gate leads to a negative threshold voltage shift, which is opposed to the positive shift caused by quantization effect in the channel. Quantization effects in the poly gate are investigated using the density gradient method, and the impact on the short channel effect of double gate device is more significant.

• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.45-49
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• 2007

The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.1-6
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• 2002

For an optimum device design of nano-scale SOI devices, this paper describes the short channel effects of multi-gate structures SOI MOSFETs such as double gate, triple gate and quadruple gate, as well as a new proposed Pi gate using computer simulation. The simulation has been performed with different channel doping concentrations, channel widths, silicon film thickness, and vertical gate extension depths of Pi gate. From the simulation results, it is found that Pi gate devices have a large margin in determination of doping concentrations, channel widths and film thickness comparing to double and triple gate devices because Pi gate devices offer a better short channel effects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.136-147
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• 2009

In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.252-255
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• 2013

Nano MOS with $Er_2O_3/SiO_2$ double-layer gate dielectrics was demonstrated by EDISON Nanophysics software. Double-layer structure decreases the gate leakage current in two orders compared with $SiO_2$ single-layer gate dielectric.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.17-24
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• 2004

Quantum effects in the poly-gate are analyzed in two dimensions using the density-gradient method, and their impact on the short-channel effect of double-gate MOSFETs is investigated. The 2-D effects of quantum mechanical depletion at the gate to sidewall oxide is identified as the cause of large charge-dipole formation at the corner of the gate. The bias dependence of the charge dipole shows that the magnitude of the dipole peak-value increases in the subthreshold region and there is a large difference in carrier and potential distribution compared to the classical solution. Using evanescent-nude analysis, it is found that the quantum effect in the poly-gate substantially increases the short-channel effect and it is more significant than the quantum effect in the Si film. The penetration of potential contours into the poly-gate due to the dipole formation at the drain side of the gate corner is identified as the reason for the substantial increase in short-channel effects.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.379-383
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• 2003

The subthreshold characteristics of Double-Gate MOSFETs are analyzed for various Tsi. In the lightly-doped asymmetric device, it is found that the subthreshold current dramatically increases as the Tsi increases and this phenomenon is due to the linear distribution of potential in the channel region with low depletion-charge. Further, we derived an analytical equation which can explain this phenomenon and verified the accuracy of analytical equation by comparing with the result of device simulation.