• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.325-330
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• 2012

In this paper, drain induced barrier lowering(DIBL) has been analyzed as one of short channel effects occurred in double gate(DG) MOSFET to be next-generation devices. Since Gaussian function been used as carrier distribution for solving Poisson's equation to obtain analytical solution of potential distribution, we expect our results using this model agree with experimental results. DIBL has been investigated according to projected range and standard projected deviation as variables of Gaussian function, and channel structure and channel doping intensity as device parameter. Since the validity of this analytical potential distribution model derived from Poisson's equation has already been proved in previous papers, DIBL has been analyzed using this model. Resultly, DIBL has been greatly changed for channel structure and doping concentration.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.127-138
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• 2013

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.793-798
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• 2012

In this paper, dependence of subthreshold current has been analyzed for doping distribution and channel structure of double gate(DG) MOSFET. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. Since DGMOSFETs have reduced short channel effects with improvement of current controllability by gate voltages, subthreshold characteristics have been enhanced. The control of current in subthreshold region is very important factor related with power consumption for ultra large scaled integration. The deviation of threshold voltage has been qualitatively analyzed using the changes of subthreshold current for gate voltages. Subthreshold current has been influenced by doping distribution and channel dimension. In this study, the influence of channel length and thickness on current has been analyzed according to intensity and distribution of doping.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.693-695
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• 2012

This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.805-811
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• 2012

In this paper, movement of conduction path has been analyzed for electron distribution in the channel of double gate(DG) MOSFET. The analytical potential distribution model of Poisson equation, validated in previous researches, has been used to analyze transport characteristics. DGMOSFETs have the adventage to be able to reduce short channel effects due to improvement for controllability of current by two gate voltages. Since short channel effects have been occurred in subthreshold region including threshold region, the analysis of transport characteristics in subthreshold region is very important. Also transport characteristics have been influenced on the deviation of electron distribution and conduction path. In this study, the influence of electron distribution on conduction path has been analyzed according to intensity and distribution of doping and channel dimension.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.748-751
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• 2014

This paper has analyzed threshold voltage movement for channel doping concentration of asymmetric double gate(DG) MOSFET. The asymmetric DGMOSFET is generally fabricated with low doping channel and fully depleted under operation. Since impurity scattering is lessened, asymmetric DGMOSFET has the adventage that high speed operation is possible. The threshold voltage movement, one of short channel effects necessarily occurred in fine devices, is investigated for the change of channel doping concentration in asymmetric DGMOSFET. The analytical potential distribution of series form is derived from Possion's equation to obtain threshold voltage. The movement of threshold voltage is investigated for channel doping concentration with parameters of channel length, channel thickness, oxide thickness, and doping profiles. As a result, threshold voltage increases with increase of doping concentration, and that decreases with decrease of channel length. Threshold voltage increases with decrease of channel thickness and bottom gate voltage. Lastly threshold voltage increases with decrease of oxide thickness.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.41-44
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• 2022

In this study, we have fabricated and characterized vertical double-gate (DG) InGaAs tunnel field-effect-transistors (TFETs) with Al₂O₃/HfO₂ = 1/5 nm bi-layer gate dielectric by employing a top-down approach. The device exhibited excellent characteristics including a minimum subthreshold swing of 60 mV/decade, a maximum transconductance of 141 µS/㎛, and an on/off current ratio of over 10³ at 20℃. Although the TFETs were fabricated using a dry etch-based top-down approach, the values of DIBL and hysteresis were as low as 40 mV/V and below 10 mV, respectively. By evaluating the effects of constant voltage and hot carrier injection stress on the vertical DG InGaAs TFET, we have identified the dominant charge trapping mechanism in TFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.5
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• pp.982-988
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• 2012

This paper has presented the relation of scaling theory and threshold voltage of double gate(DG) MOSFET. In the case of conventional MOSFET, current and switching frequency have been analyzed based on scaling theory. To observe the possibility of application of scaling theory for threshold voltage of DGMOSFET, the change of threshold voltage has been observed and analyzed according to scaling theory. The analytical potential distribution of Poisson equation has been used, and this model has been already verified. To solve Poisson equation, charge distribution such as Gaussian function has been used. As a result, it has been observed that threshold voltage is grealty changed according to scaling factor and change rate of threshold voltages is traced for scaling of doping concentration in channel. This paper has explained for the best modified scaling theory reflected the influence of two gates as using weighting factor when scaling theory has been applied for channel length and channel thickness.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.3
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• pp.571-576
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• 2016

Asymmetric double gate(DG) MOSFET has the different top and bottom gate oxides thicknesses. It is analyzed the deviation of subthreshold swing(SS) and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric DGMOSFET. SS varied along with conduction path, and conduction path varied with top and bottom gate oxide thickness. The asymmetric DGMOSFET became valuable device to reduce the short channel effects like degradation of SS. SSs were obtained from analytical potential distribution by Poisson's equation, and it was analyzed how the ratio of top and bottom oxide thickness influenced on conduction path and SS. SSs and conduction path were greatly influenced by the ratio of top and bottom gate oxide thickness. Bottom gate voltage cause significant influence on SS, and SS are changed with a range of 200 mV/dec for $0<t_{ox2}/t_{ox1}<5$ under bottom voltage of 0.7 V.