• Journal of Power Electronics
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• v.18 no.6
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• pp.1889-1900
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• 2018

Harmonic current mitigation is vital in power distribution networks owing to the inflow of nonlinear loads, distributed generation, and renewable energy sources. The active power filter (APF) is the current electrical equipment that can dynamically compensate for harmonic distortion and eliminate asymmetrical loads. The compensation performance of an APF largely depends on the control strategy applied to the voltage source inverter (VSI). Model predictive control (MPC) has been demonstrated to be one of the effective control approaches to providing fast dynamic responses. This approach covers different types of power converters due to its several advantages, such as flexible control scheme and simple inclusion of nonlinearities and constraints within the controller design. In this study, a finite control set-MPC technique is proposed for the control of VSIs. Unlike conventional control methods, the proposed technique uses a discrete time model of the shunt APF to predict the future behavior of harmonic currents and determine the cost function so as to optimize current errors through the selection of appropriate switching states. The viability of this strategy in terms of harmonic mitigation is verified in MATLAB/Simulink. Experimental results show that MPC performs well in terms of reduced total harmonic distortion and is effective in APFs.

• Journal of Power Electronics
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• v.19 no.2
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• pp.529-539
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• 2019

The modular multilevel converter (MMC) has become a promising topology for high-voltage direct current (HVDC) transmission systems. To control a MMC system properly, the ac-side current, circulating current and submodule (SM) capacitor voltage are taken into consideration. This paper proposes a low-computation indirect model predictive control (IMPC) strategy that takes advantages of the conventional MPC and has no weighting factors. The cost function and duty cycle are introduced to minimize the tracking error of the ac-side current and to eliminate the circulating current. An optimized merge sort (OMS) algorithm is applied to keep the SM capacitor voltages balanced. The proposed IMPC strategy effectively reduces the controller complexity and computational burden. In this paper, a discrete-time mathematical model of a MMC system is developed and the duty ratio of switching state is designed. In addition, a simulation of an eleven-level MMC system based on MATLAB/Simulink and a five-level experimental setup are built to evaluate the feasibility and performance of the proposed low-computation IMPC strategy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.76-88
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• 1998

While most of the research on reinforcement learning assumed a discrete control space, many of the real world control problems need to have continuous output. This can be achieved by using continuous mapping functions for the value and action functions of the reinforcement learning architecture. Two questions arise here however. One is what sort of function representation to use and the other is how to determine the amount of noise for search in action space. The ubiquitous neural network is used here to learn the value and policy functions. Next, the reinforcement predictor that is intended to predict the next reinforcement is introduced that also determines the amount of noise to add to the controller output. The proposed reinforcement learning architecture is found to have a sound on-line learning control performance especially at high-speed road following of high curvature road. Both computer simulation and actual experiments on a test vehicle have been performed and their efficiency and effectiveness has been verified.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.5
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• pp.437-443
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• 2015

This paper presents face recognition based on the fusion of visible image and thermal infrared (IR) texture estimated from the face image in the visible spectrum. The proposed face recognition scheme uses a multi- layer neural network to estimate thermal texture from visible imagery. In the training process, a set of visible and thermal IR image pairs are used to determine the parameters of the neural network to learn a complex mapping from a visible image to its thermal texture in the low-dimensional feature space. The trained neural network estimates the principal components of the thermal texture corresponding to the input visible image. Extensive experiments on face recognition were performed using two popular face recognition algorithms, Eigenfaces and Fisherfaces for NIST/Equinox database for benchmarking. The fusion of visible image and thermal IR texture demonstrated improved face recognition accuracies over conventional face recognition in terms of receiver operating characteristics (ROC) as well as first matching performances.

• Journal of the Korean Institute of Intelligent Systems
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• v.17 no.3
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• pp.285-290
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• 2007

In this paper, we presents robust digital redesign (DR) method for observer-based linear time-invariant (LTI) system. The term of DR involves converting an analog controller into an equivalent digital one by considering two condition: state-matching and stability. The design problems viewed as a convex optimization problem that we minimize the error of the norm bounds between interpolated linear operators to be matched. Also, by using the bilinear and inverse bilinear approximation method, we analyzed the uncertain parts of given observer-based system more precisely, When a sampling period is sufficiently small, the conversion of a analog structured uncertain system to an equivalent discrete-time system have proper reason. Sufficiently conditions for the state-matching of the digitally controlled system are formulated in terms of linear matrix inequalities (LMIs).

• Smart Structures and Systems
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• v.15 no.3
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• pp.627-643
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• 2015

Negative stiffness, previously emulated by active or semi-active control for cable vibration mitigation, is realized passively using a self-contained highly compressed spring, the negative stiffness device (NSD).The NSD installed in parallel with a viscous damper (VD) in the vicinity of cable anchorage, enables increment of damper deformation during cable vibrations and hence increases the attainable cable damping. Considering the small cable displacement at the damper location, even with the weakening device, the force provided by the NSD-VD assembly is approximately linear. Complex frequency analysis has thus been conducted to evaluate the damping effect of the assembly on the cable; the displacement-dependent negative stiffness is further accounted by numerical analysis, validating the accuracy of the linear approximation for practical ranges of cable and NSD configurations. The NSD is confirmed to be a practical and cost-effective solution to improve the modal damping of a cable provided by an external damper, especially for super-long cables where the damper location is particularly limited. Moreover, mathematically, a linear negative stiffness and viscous damping assembly has proven capability to represent active or semi-active control for simplified cable vibration analysis as reported in the literature, while in these studies only the assembly located near cable anchorage has been addressed. It is of considerable interest to understand the general characteristics of a cable with the assembly relieving the location restriction, since it is quite practical to have an active controller installed at arbitrary location along the cable span such as by hanging an active tuned mass damper. In this paper the cable frequency variations and damping evolutions with respect to the arbitrary assembly location are then evaluated and compared to those of a taut cable with a viscous damper at arbitrary location, and novel frequency shifts are observed. The characterized complex frequencies presented in this paper can be used for preliminary damping effect evaluation of an adaptive passive or semi-active or active device for cable vibration control.