• Korean Journal of Clinical Laboratory Science
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• v.53 no.2
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• pp.158-164
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• 2021

Hypertriglyceridemia is the main risk factor for atherosclerosis. It is reported that triglyceride (TG) induces macrophage cell death, and is involved in the formation of plaques and development of atherosclerosis. We previously reported that TG-induced cell death of macrophages is mediated via pannexin-1 activation, which increases the extracellular ATP and subsequent increase in potassium efflux, thereby activating the caspase-2/caspase-1/apoptotic caspases, including the caspase-8 pathway. Contrarily, some studies have reported that caspase-8 is an upstream molecule of caspase-1 and caspase-2 in several cellular processes. Therefore, this study was undertaken to investigate whether caspase-8 influences its upstream molecules in TG-stimulated macrophage cell death. We first confirmed that caspase-8 induces caspase-3 activation and poly ADP-ribose polymerase (PARP) cleavage in TG-treated macrophages. Next, we determined that the inhibition of caspase-8 results in reduced caspase-1 and -2 activity, which are upstream molecules of caspase-8 in TG-induced cell death of macrophages. We also found that ATP treatment restores the caspase-8 inhibitor-induced caspase-2 activity, thereby implying that caspase-8 affects the upstream molecules responsible for increasing the extracellular ATP levels in TG-induced macrophage cell death. Taken together, these findings indicate that caspase-8 potentiates the TG-induced macrophage cell death by activating its upstream molecules.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.443-451
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• 2010

This paper describes a fully integrated CMOS low-IF mobile-TV RF tuner for Band-III T-DMB/DAB applications. All functional blocks such as low noise amplifier, mixers, variable gain amplifiers, channel filter, phase locked loop, voltage controlled oscillator and PLL loop filter are integrated. The gain of LNA can be controlled from -10 dB to +15 dB with 4-step resolutions. This provides a high signal-to-noise ratio and high linearity performance at a certain power level of RF input because LNA has a small gain variance. For further improving the linearity and noise performance we have proposed the RF VGA exploiting Schmoock's technique and the mixer with current bleeding, which injects directly the charges to the transconductance stage. The chip is fabricated in a 0.18 um mixed signal CMOS process. The measured gain range of the receiver is -25~+88 dB, the overall noise figure(NF) is 4.02~5.13 dB over the whole T-DMB band of 174~240 MHz, and the measured IIP3 is +2.3 dBm at low gain mode. The tuner rejects the image signal over maximum 63.4 dB. The power consumption is 54 mW at 1.8 V supply voltage. The chip area is $3.0{\times}2.5mm^2$.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.26 no.1
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• pp.17-26
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• 2008

The 1st order level network of Korea was adjusted simultaneously in 1987. After that, the 1 st order level network of Korea was adjusted simultaneously by National Geographic Information Institute in 2006. The levelling data were acquired by digital level with invar staff from 2001 through 2006. The 1st order level network consists of 36 level lines. Among them, 34 level lines comprise 11 level loops. Among 36 level lines, 4 level lines have fore & back error larger than the regulations for the 1st order levelling of NGII, Korea. Also, the closing error of 3 loops of level network exceed the regulation for the 1st order levelling of NGII. The standard error of fore and back leveling between bench marks(${\eta}_1$) are distributed between 0.2 $mm/{\surd}km$ and 1.7 $mm/{\surd}km$. The standard error of loop closing(${\eta}_2$) is 2.0 $mm/{\surd}km$. This result means that the 1st order level network of Korea qualifies for the high precision leveling defined by International Geodetic Association in 1948. As the result of the 1st order level network adjustment, the reference standard error($\hat{{\sigma}_0}$) of the level network was 1.8 $mm/{\surd}km$, which is twice as good as that of the 1st adjustment of level networks in 1987.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.411-414
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• 2008

The study is about simulation of optical circuit for oneself performance evaluation of Fiber Optic Gyro(FOG) closed-loop controller board. The Fiber Optic Interferometer Simulator is used a digital signal processing for cosine response specificity output of fiber optic coil about input rate. Response specificity of the fiber optic coil is $Vo(t)=K3[1+\cos\{K1(Vm(t)-Vm(t-{\tau}))+K2\}]$. Also the Fiber Optic Interferometer Simulator is able to confirm a output value with K1, K2 and K3 input. The fiber Optic Interferometer Simulator is able to oneself performance evaluation without fiber optical circuit. Because, it is the very same cosine response specificity of real fiber optic coil about input rate.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.2
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• pp.95-99
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• 2005

This paper presents an accurate recovery method of the reference clock which is needed for network synchronization in two-way satellite multimedia systems compliant with DVB-RCS specification and which use closed loop method for burst synchronization. In these systems, the remote station transmits TDMA burst via return link. For burst synchronization, it obtains reference clock from program clock reference (PCR) defined by MPEG-2 system specification. The PCR is generated periodically at the hub system by sampling system clock which runs at 27MHz $\pm$ 30ppm. Since the reference clock is recovered by means of digital PLL(DPLL) using imprecise PCR values due to variable random jitter, the recovered clock frequency of remote station doesn't exactly match reference clock of hub station. We propose a robust recovery method of reference clock against random delay jitter The simulation results show that the recovery error is remarkably decreased from 5 clocks to 1 clock of 27MHz relative to the general DPLL recovery method.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.3
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• pp.1-7
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• 2002

This paper presents a new PLL clock generator that can improve a jitter noise characteristics and acquisition process by designing a multi-PFD(Phase Frequency Detector) and an adaptive charge pump circuit. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. An advanced multi-structured PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, in which it shows an excellent functionalities in terms of the jitter noises by designing its circuit with the exact dead zone and duty cycle. Our new designed adaptive charge pump in the loop filter of a PLL can improve an acquisition characteristic by adaptively increasing of current. The Hspice simulation is done to evaluate the performance of the proposed circuit. Simulation result shows that our PLL has under 0.01ns in the dead zone, no influence from the duty cycle of input signals and under 50ns in the acquisition time. This circuit will be able to be used in develops of high-performance microprocessors and digital systems.  

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.429-430
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• 2008

본 논문은 전기출력이 1400 MWe급으로 개발된 첨단 원자력 발전소인 APR1400(신형겨수로 1400) 제어계통에 적용되는 디지털시스템의 설계 및 성능 검증을 위해 개발 중인 디지털제어계통 검증시스템에 관한 것이다. APR1400 디지털제어계통은 발전소 출력 제어 및 안전운전과 관련 된 중요 기능들을 수행하며, 기존 원자력발전소와 달리 단일 디지털 Platform을 적용하고, Multi-Loop 개념과 네트워크을 적용하여 Controller와 케이블 수량을 줄인 특징을 가지고 있다. 이와 같을 설계는 지금가지 원자력발전소에는 적용된 적이 없기 때문에 사용자 측면에서는 디지털 제어 계통 설계 및 성능 관점에서의 검증을 위한 시스템이 요구되었다. 현재는 APR1400 시뮬레이터(발전소 모델링을 통한 모의시스템)를 이용한 검증시스템을 1차적으로 구축한 상태에 있으며, 시스템 전체 시험을 진행 중에 있다. 특히, 이번에 개발 중인 검증시스템은 구성이 간단하고 사용이 편리한 장점을 지니고 있을 뿐만 아니라 다양한 고장상황을 재현해 봄으로써 디지털제어계통의 성능을 확인해 볼 수 있는 특징을 보유하고 있다. 본 검증시스템의 활용방안으로는 첫째, 계통설계의 구현 가능성 관점에서의 확인시험을 수행하는 방안, 둘째, 발전소 시운전 착수 전 시운전요원 교육에 활용하는 방안, 셋째, 발전소 설계 변경 필요 시 설계 변경에 따른 영향 파악, 넷째, 디지털제어계통 유지보수 기술 습득 등에 효과적으로 활용 할 수 있을 것으로 본다. AFR1400 디지털제어계통은 현재 건설 중인 신고리 3,4호기 원자력발전소에 적용될 예정이며, 향후에는 해외 원자력 수출을 위한 기반기술로 활용될 수 있을 것으로 확신한다.