• Journal of Practical Engineering Education
• /
• v.10 no.1
• /
• pp.49-56
• /
• 2018

Various types of SW education are being operated by universities for non-major undergraduates. And most of them focus on educating computational thinking. Following this computing education, there is a need for an educational method that implements and evaluates creative computing outcomes for each student. In this paper, we propose a method to realize SW education based on creative computing artifacts. To do this, we propose an educational method for students to implement digital logic circuit devices creatively and design SW algorithms that implement the functions of their devices. The proposed training method teaches a simple LED logic circuit using an Arduino board as an example. Students creatively design and implement two pairs of two input logic circuit devices, and design algorithms that represent patterns of implemented devices in various forms. And they design the functional extension and extended algorithm using the input device. By applying the proposed method, non-major students can gain the concept and necessity of algorithm design through creative computing artifacts.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.1-10
• /
• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.26 no.6
• /
• pp.87-93
• /
• 2012

In this paper, we propose an analog-to-digital converter to set the address of a I2C slave chip. The proposed scheme converts a fixed voltage between 0 and VDD to the digital value which can be used as the address of the slave chip. The rising time and the falling time are measured with digital counter in a serially connected RC circuit, while the circuit is being charged and discharged with the voltage to be measured. The ratio of the two measured values is used to get the corresponding digital value. This scheme gives a strong point which is to be implementable all the parts except comparator using digital logic. Although the method utilizes RC circuit, it has no relation with the RC value if the quantization error is disregarded. Experimental result shows that the proposed scheme gives 32-level resolution thus it can be used to configure the address of the I2C slave chip.

• Proceedings of the KIEE Conference
• /
• 1993.07a
• /
• pp.501-503
• /
• 1993

A circuit of sigmoid function for neural network is designed by using Piecewise Linear (PWL) method. The slope of sigmoid function can be adjusted to 2 and 0.25. Also the circuit presents both sigmoid function and its differential form. The circuits is simulated by using ViewLogic. Theoretical and simulated performance agree with 1.8 percent.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.1C
• /
• pp.8-13
• /
• 2011

In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.15 no.12 s.91
• /
• pp.1161-1167
• /
• 2004

The conventional PLL(phase locked loop) frequency synthesizer takes a long switching time because of the inherent closed-loop structure. The digital hybrid PLL(DH-PLL) which includes the open-loop structure into the conventional PLL synthesizer has been studied to overcome this demerit. It operates in high speed, but the hardware complexity and power consumption are the serious problem because the DLT(digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO(voltage controlled oscillator). This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT. Also, a timing synchronization circuit for the very small over-shoot and shorter settling time is designed for the ultra fast switching speed at every frequency synthesis. The hardware complexity gets decreased to about $28\%,$ as compared with the conventional DH-PLL. The high speed switching characteristic of the frequency synthesis process can be verified by the computer simulation and the circuit implementation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.10
• /
• pp.1794-1800
• /
• 2008

This paper presents a method of constructing the digital logic switching functions using PLA. First of all, we propose a MIN and MAX algebra arithmetic operation based on the Post algebra. And we discuss the T-gate which is used for realization of the MIN and MAX algebra arithmetic operation. Next, we discuss the MIN array and MAX array which are basic circuit of the PLA, also we discuss the literal property. For the purpose of the design for the digital logic switching functions using PLA, we Propose the variable partition, modular structure design, literal generator, decoder and invertor. The proposed method is the more compactable and extensibility.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.3
• /
• pp.506-514
• /
• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• Journal of Engineering Education Research
• /
• v.2 no.1
• /
• pp.10-16
• /
• 1999

In this paper, we developed the internet-based educational software package (DVLab) for design and virtual experiment of the digital logic circuits. The DVLab consists of the LogicSim module for design and simulation of digital combinational/sequantial logic circuits, micro-controller application circuits and the BreadBoard module for virtual experiment and the Theory module for lecture and the Report/ReportChecker module and some other utility modules. All developed modules can be run as application programs as well as applets in the Internet. The LogicSim and the BreadBoard support real time clock function, output verification function on the designed circuits, trace function of logic values, copy-protection function of designed circuits and provide various devices including logic gates, TTLs, LED, buzzer, and micro-controller. The educational model of digital logic circuit design and experiment using the DVLab is also presented in this paper.

• Proceedings of the IEEK Conference
• /
• 2001.06e
• /
• pp.5-8
• /
• 2001

In this paper, we have space vector PWM(Pulse Width Modulation) circuits on the FPGA(Field Programmable Gate Arry) chip designed by VHDL(Very high speed integrated circuit Hardware Description Language). This circuit parts was required at controlling the AC servo motor system and should have been designed with many discrete digital logics. In the result of this study, peripheral circuits are to be simple and the designed logic terms are robust and precise. Because of it's easy verification and implementation, we could deduced that the customize FPGA chip show better performance than that of circuit modules parts constituted of discrete IC.